
24-18
MPC561/MPC563 Reference Manual
MOTOROLA
Programming Model
NOTE
There is no way to distinguish between off-core MPC500
special purpose register (SPR) map and normal memory map
accesses via the defined address range control. If data trace
ranges are set up such that the off-core MPC500 SPR map falls
within active ranges, then accesses to these off-core MPC500
SPRs will be traced, and the messages will not be
distinguishable from accesses to normal memory map space.
Off-core MPC500 SPRs typically exist in the 8- to 16-Kbyte
lowest memory block (0x2000 – 0x3FF0). If data or
peripherals are mapped to this space, load/stores to MPC500
SPRs will be indistinguishable from data or peripheral
accesses.
24.6.2
Accessing Memory-Mapped Locations Via
the Auxiliary Port
The control and status information is accessed via the four auxiliary access public
messages: device ready for upload/download, upload request (tool requests information),
download request (tool provides information), and upload/download information
(device/tool provides information).
Table 24-15. DTA 1 AND 2 Bit Descriptions
RCPU
Bits
Nexus
Bits
Name
Description
0:22
47:25
DTEA 1
1 Data trace range start and end addresses must be word-aligned.
The Read/Write End Field defines the end address for the address range. Refer to
23:45
24:2
The Read/Write Start Field defines the starting address for the address range.
46:47
1:0
TA
The Read/Write Trace Field can be configured to allow enabling or disabling data read
and/or data write traces.
00 Disable data read and data write trace
x1 Enable data read trace
1x Enable data write trace
Table 24-16. Data Trace Values
Programmed Values
Range Selected
DTSA < DTEA
DTSA
→
← DTEA
DTSA > DTEA
Invalid Range
DTSA = DTEA
Word at DTSA