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參數(shù)資料
| 型號： | MPC5606SVLU6R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件頁數(shù)： | 48/136頁 |
| 文件大?。?/td> | 858K |
| 代理商： | MPC5606SVLU6R |
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
19
— Provides a clock for rapid start-up from low power modes
— Provides a back-up clock in the event of PLL or External Oscillator clock failure
— Offers an independent clock source for the Watchdog timer
— ±5% accuracy across voltage and temperature (after factory trimming)
— Trimming registers to support frequency adjustment with in-application calibration
1.6.20
Periodic Interrupt Timer module (PIT)
The PIT features the following:
4 general purpose interrupt timers
Up to 2 dedicated interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by system clock frequency
32-bit counter for Real Time Interrupt, clocked from main external oscillator
1.6.21
Real Time Counter (RTC)
Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation
Configurable resolution for different timeout periods
— 1 s resolution for >1 hour period
— 1 ms resolution for 2 second period
Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal 128 kHz RC oscillator or
divided internal 16 MHz RC oscillator
1.6.22
System Timer Module (STM)
The STM is a 32-bit timer designed to support commonly required system and application software timing functions. The STM
includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is
driven by the system clock divided by an 8-bit prescale value (1 to 256).
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.6.23
Software Watchdog Timer (SWT)
The Watchdog features the following:
Watchdog supporting software activation or enabled out of Reset
Supports normal or windowed mode
Watchdog timer value writable once after reset
Watchdog supports optional halting during low power modes
Configurable response on timeout: reset, interrupt, or interrupt followed by reset
Selectable clock source for main system clock or internal 16 MHz RC oscillator clock
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