參數(shù)資料
型號： MPC5604PGF0MLQ4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 9/99頁
文件大?。?/td> 1130K
代理商： MPC5604PGF0MLQ4
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
17
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
— External event counting: max. count rate = peripheral clock/2
— Internal clock counting: max. count rate = peripheral clock
Counters are:
— Cascadable
— Preloadable
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Pins available as GPIO when timer functionality not in use
1.5.27
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
2 on-chip AD converters
— 10-bit AD resolution
— 1 sample and hold unit per ADC
— Conversion time, including sampling time, less than 1 s (at full precision)
— Typical sampling time is 150 ns min. (at full precision)
— Differential non-linearity error (DNL) ±1 LSB
— Integral non-linearity error (INL) ±1.5 LSB
—TUE <3 LSB
— Single-ended input signal up to 5.0 V
— The ADC and its reference can be supplied with a voltage independent from VDDIO
— The ADC supply can be equal or higher than VDDIO
— The ADC supply and the ADC reference are not independent from each other (they are internally bonded to the
same pad)
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part:
2 × 13 input channels including 4 channels shared between the 2 converters
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location,
2 modes of operation: Normal mode or CTU control mode
Normal mode features
— Register-based interface with the CPU: control register, status register, 1 result register per channel
相關(guān)PDF資料
PDF描述
MPC5604PEF0MLL6 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
MPC5604PGF0VLL6R 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
MPC5604PEF0VLL4R 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100
MPC5604PFF0VLQ6R 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
MPC5604PEF0MLL4 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100
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