參數(shù)資料
型號(hào)： MPC5604PFF0VLQ4R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁(yè)數(shù)： 11/99頁(yè)
文件大?。?/td> 1130K
代理商： MPC5604PFF0VLQ4R
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
19
— Watchpoint triggering, watchpoint triggers program tracing
Auxiliary Output Port
— 4 MDO (Message Data Out) pins
— MCKO (Message Clock Out) pin
—2 MSEO (Message Start/End Out) pins
—EVTO (Event Out) pin
Auxiliary Input Port
—EVTI (Event In) pin
1.5.30
Cyclic redundancy check (CRC)
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:
Support for CRC-16-CCITT (x25 protocol):
— x16 + x12 + x5 + 1
Support for CRC-32 (Ethernet protocol):
— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
1.5.31
IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.
The JTAGC block is compliant with the IEEE standard.
The JTAG controller provides the following features:
IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO)
Selectable modes of operation include JTAGC/debug or normal system operation.
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE
3 test data registers: a bypass register, a boundary scan register, and a device identification register.
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry.
1.5.32
On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
Uses external NPN (negative-positive-negative) transistor
Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic
Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
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