參數(shù)資料
型號(hào)： MPC5604PEF0VLL4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100
文件頁(yè)數(shù)： 70/99頁(yè)
文件大?。?/td> 1130K
代理商： MPC5604PEF0VLL4
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
72
Figure 18. Pad output delay
ttr
CC D Output transition time output pin2
MEDIUM configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
——
10
ns
TCL = 50 pF
—
20
DCL = 100 pF
—
40
DCL = 25 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
——
12
TCL = 50 pF
—
25
DCL = 100 pF
—
40
ttr
CC D Output transition time output pin2
FAST configuration
CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
——
4
ns
CL = 50 pF
—
6
CL = 100 pF
—
12
CL = 25 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
——
4
CL = 50 pF
—
7
CL = 100 pF
—
12
tSYM
3
CC T Symmetric transition time, same drive
strength between N and P transistor
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
4
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
5
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2 C
L includes device and package capacitances (CPKG < 5 pF).
3 Transition timing of both positive and negative slopes will differ maximum 50%
Table 34. Output pin transition times (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min Typ Max
VDD_HV_IOx/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
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