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參數(shù)資料
| 型號(hào)： | MPC5604PEF0MLL6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100 |
| 文件頁(yè)數(shù)： | 49/99頁(yè) |
| 文件大?。?/td> | 1130K |
| 代理商： | MPC5604PEF0MLL6 |
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MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
53
Figure 12. Brown-out typical sequence
3.10
DC electrical characteristics
3.10.1
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the non-volatile user options (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference manual.
3.10.1.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 17 shows how NVUSRO[PAD3V5V]
controls the device configuration.
3.10.1.2
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 18 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 17. PAD3V5V field description
Value1
1 Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR
0V
1.2V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV)
3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0
IDLE
0V
1.2V
Internal Reset Generation Module
FSM
VLVDHV3L
0V
VLVDHV3H
P1
~1us
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