參數(shù)資料
型號(hào)： MPC5604CF1VMG4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, MO-151AAF-1, MAPBGA-208
文件頁(yè)數(shù)： 53/104頁(yè)
文件大?。?/td> 953K
代理商： MPC5604CF1VMG4
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor
52
The
VDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the component used for the VDD supply
generation. The following two examples describe how to calculate capacitance size:
Example 1. No regulator (worst case)
The
VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR resistance of the regulator stability
capacitor when the IDD_BV current required to load VDD_LV domain during the standby exit. It is thus possible to define the
maximum equivalent resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply:
ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1 1
The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance pin (excluding ESR drop) while
providing the IDD_BV supply required to load VDD_LV domain during the standby exit. It is thus possible to define the minimum
equivalent capacitance CSTDBY(MIN) of the total capacitance on the VDD supply:
CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/s) = 20 F
This configuration is a worst case, with the assumption no regulator is available.
Example 2. Simplified regulator
The regulator should be able to provide significant amount of the current during the standby exit process. For example, in case
of an ideal voltage regulator providing 200 mA current, it is possible to recalculate the equivalent ESRSTDBY(MAX) and
CSTDBY(MIN) as follows:
ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV 200 mA) = (30 mV)/(100 mA) = 0.3
CSTDBY(MIN) = (IDD_BV 200 mA)/dVDD(STDBY)/dt = (300 mA 200 mA)/(15 mV/s) = 6.7 F
In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated based on the regulator
characteristics as well as the board VDD plane characteristics.
4.9.2
Low voltage detector electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage
detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
IDD_BV
CC D In-rush average current on VDD_BV
during power-up5
——
—
3006
mA
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2 This capacitance value is driven by the constraints of the external voltage regulator supplying the V
DD_BV voltage.
A typical value is in the range of 470 nF.
3 This value is acceptable to guarantee operation from 4.5 V to 5.5 V
4 External regulator and capacitance circuitry must be capable of providing I
DD_BV while maintaining supply VDD_BV
in operating range.
5 In-rush average current is seen only for short time (maximum 20 s) during power-up and on standby exit. It is
dependant on the sum of the CREGn capacitances.
6 The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
1. Based on typical time for standby exit sequence of 20 s, ESR(MIN) can actually be considered at ~50 kHz.
Table 25. Voltage regulator electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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