參數(shù)資料
型號(hào)： MPC5604CF1MMG4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, MO-151AAF-1, MAPBGA-208
文件頁(yè)數(shù)： 102/104頁(yè)
文件大小： 953K
代理商： MPC5604CF1MMG4
Document revision history
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
97
2
06-Mar-2009 Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Features:
—Replaced 32 KB with 48 KB as max SRAM size
—Updated description of INTC
—Changed max number of GPIO pins from 121 to 123
Updated Section 1.2, Descrioption
Updated Table 2
Added Section 2, “Block diagram
Section 3, “Package pinouts and signal descriptions: Removed signal descriptions (these
are found in the device reference manual)
Updated Figure 5:
—Replaced VPP with VSS_HV on pin 18
—Added MA[1] as AF3 for PC[10] (pin 28)
—Added MA[0] as AF2 for PC[3] (pin 116)
—Changed description for pin 120 to PH[10] / GPIO[122] / TMS
—Changed description for pin 127 to PH[9] / GPIO[121] / TCK
—Replaced NMI[0] with NMI on pin 11
Updated Figure 4:
—Replaced VPP with VSS_HV on pin 14
—Added MA[1] as AF3 for PC[10] (pin 22)
—Added MA[0] as AF2 for PC[3] (pin 77)
—Changed description for pin 81 to PH[10] / GPIO[122] / TMS
—Changed description for pin 88 to PH[9] / GPIO[121] / TCK
—Removed E1UC[19] from pin 76
—Replaced [11] with WKUP[11] for PB[3] (pin 1)
—Replaced NMI[0] with NMI on pin 7
Updated Figure 6:
—Changed description for ball B8 from TCK to PH[9]
—Changed description for ball B9 from TMS to PH[10]
—Updated descriptions for balls R9 and T9
Added Section 4.2, “Parameter classification and tagged parameters in tables where
appropriate
Added Section 4.3, “NVUSRO register
Updated Table 5
Section 4.5, “Recommended operating conditions: Added note on RAM data retention to
end of section
Updated Table 6 and Table 7
Added Section 4.6.1, “Package thermal characteristics
Updated Section 4.6.2, “Power considerations
Updated Figure 7
Updated Table 9, Table 10, Table 11, Table 12 and Table 13
Added Section 4.7.4, “Output pin transition times
Updated Table 16
Updated Figure 8
Updated Table 18
Section 4.9.1, “Voltage regulator electrical characteristics: Amended description of
LV_PLL
Figure 10: Exchanged position of symbols CDEC1 and CDEC2
Updated Table 19
Table 49. Revision history (continued)
Revision
Date
Description of Changes
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