參數(shù)資料
型號： MPC5604CF1CLQ6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
文件頁數(shù)： 32/104頁
文件大小： 953K
代理商： MPC5604CF1CLQ6
Electrical characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
33
4.5
Recommended operating conditions
Table 12. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
V
VDD
1
1 100 nF capacitance needs to be provided between each V
DD/VSS pair
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—3.0
3.6
V
VSS_LV
2
2 330 nF capacitance needs to be provided between each V
DD_LV/VSS_LV supply pair.
SR Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_BV
3
3 400 nF capacitance needs to be provided between V
DD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—3.0
3.6
V
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_ADC
4
4 100 nF capacitance needs to be provided between V
DD_ADC/VSS_ADC pair.
SR Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)
—3.05
5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
3.6
V
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to ground
(VSS)
—VSS0.1
—
V
Relative to VDD
—VDD+0.1
IINJPAD
SR Injected input current on any pin during overload
condition
—
55
mA
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
—
50
TVDD
SR VDD slope to ensure correct power up
6
6 Guaranteed by device validation
—
0.25
V/s
TA C-Grade Part SR Ambient temperature under bias
fCPU 64 MHz
40
85
°C
TJ C-Grade Part SR Junction temperature under bias
40
110
TA V-Grade Part SR Ambient temperature under bias
40
105
TJ V-Grade Part SR Junction temperature under bias
40
130
TA M-Grade Part SR Ambient temperature under bias
40
125
TJ M-Grade Part SR Junction temperature under bias
40
150
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