MPC5604P Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
42
Figure 7. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
VA
VA1
VA2
t
TS
VCS
Voltage Transient on CS
ΔV < 0.5 LSB
1
2
τ
1 < (RSW + RAD) CS << TS
τ
2 = RL (CS + CP1 + CP2)
τ1 RSW RAD
+
()
=
CP CS
CP CS
+
---------------------
τ1 RSW RAD
+
()
<
CS TS
VA1 CS CP1 CP2
++
()
VA CP1 CP2
+
()
=
τ2 RL
<
CS CP1 CP2
++
()
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