參數(shù)資料
型號(hào)： MPC5602PEF0MLL4R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100
文件頁(yè)數(shù)： 66/95頁(yè)
文件大?。?/td> 1694K
代理商： MPC5602PEF0MLL4R
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
69
3.17.2
IEEE 1149.1 interface timing
Figure 20. JTAG test clock input timing
4 CL includes device and package capacitance (CPKG <5pF).
5 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 36. JTAG pin AC electrical characteristics
No.
Symbol
C
Parameter
Conditions
Value
Unit
Min
Max
1tJCYC
CC
D TCK cycle time
—
100
—
ns
2tJDC
CC
D TCK clock pulse width (measured at VDD_HV_IOx/2)
—
40
60
ns
3tTCKRISE
CC
D TCK rise and fall times (40%–70%)
—
3
ns
4tTMSS, tTDIS CC D TMS, TDI data setup time
—
5
—
ns
5tTMSH, tTDIH CC D TMS, TDI data hold time
—
25
—
ns
6tTDOV
CC
D TCK low to TDO data valid
—
40
ns
7tTDOI
CC
D TCK low to TDO data invalid
—
0
—
ns
8tTDOHZ
CC
D TCK low to TDO high impedance
—
40
—
ns
9tBSDV
CC
D TCK falling edge to output valid
—
50
ns
10
tBSDVZ
CC
D TCK falling edge to output valid out of high
impedance
——
50
ns
11
tBSDHZ
CC
D TCK falling edge to output high impedance
—
50
ns
12
tBSDST
CC
D Boundary scan input valid to TCK rising edge
—
50
—
ns
13
tBSDHT
CC
D TCK rising edge to boundary scan input invalid
—
50
—
ns
TCK
1
2
3
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