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參數(shù)資料
| 型號： | MPC5602DVLHR |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 16/77頁 |
| 文件大小： | 686K |
| 代理商： | MPC5602DVLHR |
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Electrical characteristics
MPC5602D Microcontroller Data Sheet, Rev. 3.1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
23
NOTE
SRAM data retention is guaranteed with VDD_LV not below 1.08 V.
Table 9. Recommended operating conditions (5.0 V)
Symbol
C
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR — Digital ground on VSS_HV pins
—
0
V
VDD
1
SR — Voltage on VDD_HV pins with respect to ground
(VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
VSS_LV
3
SR — Voltage on VSS_LV (low voltage digital supply) pins
with respect to ground (VSS)
—VSS 0.1 VSS +0.1
V
VDD_BV
4
SR — Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—4.5
5.5
V
Voltage drop(2)
3.0
5.5
Relative to VDD VDD 0.1 VDD +0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with
respect to ground (VSS
—VSS 0.1 VSS +0.1
V
VDD_ADC
5 SR — Voltage on VDD_HV_ADC pin (ADC reference) with
respect to ground (VSS)
—4.5
5.5
V
Voltage drop(2)
3.0
5.5
Relative to VDD VDD 0.1 VDD +0.1
VIN
SR — Voltage on any GPIO pin with respect to ground
(VSS)
—VSS 0.1
—
V
Relative to VDD
—VDD +0.1
IINJPAD
SR — Injected input current on any pin during overload
condition
—
55
mA
IINJSUM
SR — Absolute sum of all injected input currents during
overload condition
—
50
TVDD
SR — VDD slope to ensure correct power up
6
—
TBD
0.25
V/s
TA
SR — Ambient temperature under bias
fCPU 48 MHz
40
125
°C
TJ
SR — Junction temperature under bias
—
40
150
1 100 nF capacitance needs to be provided between each V
DD/VSS pair.
2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each V
DD_LV/VSS_LV supply pair.
4 470 nF capacitance needs to be provided between V
DD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5 100 nF capacitance needs to be provided between V
DD_ADC/VSS_ADC pair.
6 Guaranteed by device validation
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