參數(shù)資料
型號： MPC5601PEF0VLH6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 42/95頁
文件大?。?/td> 1694K
代理商： MPC5601PEF0VLH6
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
47
3.10
DC electrical characteristics
3.10.1
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the non-volatile user options (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference manual.
3.10.1.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 15 shows how NVUSRO[PAD3V5V]
controls the device configuration.
3.10.1.2
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 16 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
3.10.2
DC electrical characteristics (5 V)
Table 17 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V] = 0).
Table 15. PAD3V5V field description
Value1
1 Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
Table 16. OSCILLATOR_MARGIN field description
Value1
1 Default manufacturing value before flash initialization is ‘1’.
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
Table 17. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol
C
Parameter
Conditions
Value
Unit
Min
Max
VIL
D Low level input voltage
—
0.41
—V
P—
—
0.35 VDD_HV_IOx
V
VIH
P High level input voltage
—
0.65 VDD_HV_IOx
—V
D—
—
VDD_HV_IOx +0.41 V
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—V
VOL_S
P Slow, low level output voltage
IOL =3 mA
—
0.1 VDD_HV_IOx
V
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