參數(shù)資料
型號: MPC5601PEF0MLH6
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù): 91/95頁
文件大?。?/td> 1694K
代理商: MPC5601PEF0MLH6
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
91
4
11 May 2011 Editorial and formatting changes throughout
Section 1, “Introduction: Reorganized contents
MPC5602P block diagram: reorganized blocks above and below peripheral bridge; made
arrow going from peripheral bridge to crossbar switch bidirectional
Updated Section 1.5, “Feature list:
changed core feature from “64 MHz” to “Up to 64 MHz”
memory organization
moved “16-channel eDMA controller” item to “Interrupts and events” item
LINFlex: changed “2 LINFlex modules” to “Up to 2 LINFlex modules”
DSPI: changed “3 DSPI channels“ to “Up to 3 DSPI channels”
ADC: changed “16 input channels“ to “Up to 16 input channels”
64-pin and 100-pin LQFP pinout diagrams: replaced instances of HV_AD0 with
HV_ADC0
System pins: updated “XTAL” and “EXTAL” rows
BJTs; replaced two configuration diagrams and two electrical characteristics tables
with single diagram and single table
Low voltage monitor electrical characteristics: updated VMLVDDOK_H max value—was
1.15 V; is 1.145 V
IDD_LV_CORx; changed parameter classification from T to P for IDD_LV_CORx
RUN—Maximum mode at 64 MHz; added IDD_FLASH characteristics; replaced
instances of “Airbag” mode with “Typical mode”
IDD_LV_CORx; replaced instances of “Airbag” mode with “Typical mode”
description for VOL_F—was “Fast, high level output voltage”; is “Fast, low level output
voltage”
Main oscillator output electrical characteristics tables: replaced instances of EXTAL with
XTAL; added load capacitance parameter
FMPLL electrical characteristics: updated conditions and table title; removed fsys row;
updated fFMPLLOUT values; replaced instances of VDDPLL with VDD_LV_COR0; replaced
instances of VSSPLL with VSS_LV_COR0
RCMTRIM and RCMSTEP
ADC conversion characteristics: updated symbols; added row tADC_PU
Removed section “Generic timing diagrams”
4
(cont’d)
11 May 2011 Updated Start-up reset requirements diagram
Removed FlexCAN timing characteristics
In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS
Strobe (PCSS) Timing”: added note
Table A-1: added “DUT”, “NPN”, and “RISC”
Table 40. Revision history (continued)
Revision
Date
Description of
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