參數(shù)資料
型號: MPC5554MVR132
廠商: Freescale Semiconductor
文件頁數(shù): 3/58頁
文件大小: 0K
描述: IC MCU 2M FLASH 132MHZ 416-PBGA
產品培訓模塊: MPC55xx PitchPak Family
標準包裝: 40
系列: MPC55xx Qorivva
核心處理器: e200z6
芯體尺寸: 32-位
速度: 132MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 256
程序存儲器容量: 2MB(2M x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.35 V ~ 1.65 V
數(shù)據(jù)轉換器: A/D 40x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 416-BBGA
包裝: 托盤
配用: MPC5554INT-ND - BOARD DEMO MPC5554
MPC5554EVBISYS-ND - BOARD EVAL ISYSTEMS MPC5554
MPC5554EVBGHS-ND - BOARD EVAL GREEN HILLS SOFTWARE
MPC5554EVB-ND - BOARD EVALUATION MPC5554
MPC5534EVBISYS-ND - KIT EVAL ISYSTEMS MPC5534
MPC5534EVBGHS-ND - KIT EVAL GREEN HILLS SOFTWARE
MPC5534EVB-ND - KIT EVALUATION MPC5534MZP80
MPC5554EVBE-ND - BOARD EVAL FOR MPC5554
MPC5534EVBE-ND - BOARD EVAL FOR MPC5534
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current
consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the
1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR
negates again. All oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between VRC33 and VDDSYN is required for the VRC to operate within specification.
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR
negates. When the internal POR negates, the functional state of the signal during reset applies and the
weak-pull devices
(up or down) are enabled as defined in the device reference manual. If VDD is too low to correctly
propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
Table 7. Pin Status for Fast Pads During the Power Sequence
VDDE
VDD33
VDD
POR
Pin Status for Fast Pad Output Driver
pad_fc (fast)
Low
Asserted
Low
VDDE
Low
Asserted
High
VDDE
Low
VDD
Asserted
High
VDDE
VDD33
Low
Asserted
High impedance (Hi-Z)
VDDE
VDD33
VDD
Asserted
Hi-Z
VDDE
VDD33
VDD
Negated
Functional
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
VDDEH
VDD
POR
Pin Status for Medium and Slow Pad Output Driver
pad_mh (medium) pad_sh (slow)
Low
Asserted
Low
VDDEH
Low
Asserted
High impedance (Hi-Z)
VDDEH
VDD
Asserted
Hi-Z
VDDEH
VDD
Negated
Functional
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