參數(shù)資料
型號(hào): MPC5554MVR112R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PBGA416
封裝: 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416
文件頁(yè)數(shù): 2/58頁(yè)
文件大?。?/td> 1452K
代理商: MPC5554MVR112R2
MPC5554 Microcontroller Data Sheet, Rev. 2.0
Electrical Characteristics
Freescale Semiconductor
10
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),and
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
8
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6
reach the VPOR33 and VPOR5 minimums respectively.
VDD33_LAG
—1.0
V
9
Absolute value of slew rate on power supply pins
50
V/ms
10
Required gain at Tj:
IDD ÷ IVRCCTL (@ fsys = fMAX)
5, 6, 8, 9
BETA10
– 55o C7
70
mA
– 40o C
70
25o C
——
150o C
10510
500
1 V
IL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5.
2 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
3 It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
4 At peak current for device.
5 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1
Ω). V
RCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF (nominal)
bulk capacitor (greater than 4
μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01
μF, two 0.1 μF, and one 1 μF capacitors around the package on the V
DD supply signals.
6 I
VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
7 Only available on devices that support -55o C.
8 Refer to Table 1 for the maximum operating frequency.
9 Values are based on I
DD from high-use applications as explained in the IDD Electrical Specification.
10 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
DD ÷ IVRCCTL).
Table 6. VRC/POR Electrical Specifications (continued)
Spec
Characteristic
Symbol
Min
Max
Units
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MPC5554MVR80R2 制造商:Freescale Semiconductor 功能描述:MCU 32BIT 55XX RISC 2MB FLASH 1.8V/2.5V/3.3V/5V 416BGA - Tape and Reel
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