參數(shù)資料
型號(hào)： MPC5534MZQ66
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-324
文件頁(yè)數(shù)： 40/60頁(yè)
文件大?。?/td> 1055K
代理商： MPC5534MZQ66
Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
45
3.13.9
eQADC SSI Timing
Figure 27. EQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics
Spec
Rating
Symbol
Minimum
Typical
Maximum
Unit
2
FCK period (tFCK = 1 fFCK)
1, 2
1 SS timing specified at V
DDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
tFCK
2—
17
tSYS_CLK
3
Clock (FCK) high time
tFCKHT
tSYS_CLK 6.5
—
9
(t
SYS_CLK 6.5)
ns
4
Clock (FCK) low time
tFCKLT
tSYS_CLK 6.5
—
8
(t
SYS_CLK 6.5)
ns
5
SDS lead / lag time
tSDS_LL
–7.5
—
+7.5
ns
6
SDO lead / lag time
tSDO_LL
–7.5
—
+7.5
ns
7
EQADC data setup time (inputs)
tEQ_SU
22
—
ns
8
EQADC data hold time (inputs)
tEQ_HO
1—
—
ns
1st (MSB)
2nd
25th
26th
1st (MSB) 2nd
25th
26th
8
7
5
6
4
5
4
2
3
FCK
SDS
SDO
External device data sample at
SDI
EQADC data sample at
FCK falling-edge
FCK rising-edge
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