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參數(shù)資料
| 型號： | MPC5534MVF40 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, MO-151AAF-1, MAPBGA-208 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 1055K |
| 代理商： | MPC5534MVF40 |
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Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
31
3.13.3
Nexus Timing
Figure 10. Nexus Output Timing
Table 21. Nexus Debug Port Timing 1
1 JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of
MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35–1.65 V, VDDE = 2.25–3.6 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
MCKO cycle time
tMCYC
1 2
2 The Nexus AUX port runs up to 82 MHz.
8tCYC
2
MCKO duty cycle
tMDC
40
60
%
3
MCKO low to MDO data valid 3
3 MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.
tMDOV
–1.5
3.0
ns
4
MCKO low to MSEO data valid 3
tMSEOV
–1.5
3.0
ns
5
MCKO low to EVTO data valid 3
tEVTOV
–1.5
3.0
ns
6
EVTI pulse width
tEVTIPW
4.0
—
tTCYC
7
EVTO pulse width
tEVTOPW
1—
tMCYC
8
TCK cycle time
tTCYC
4 4
4 Limit the maximum frequency to approximately 16 MHz (V
DDE = 2.25–3.0 V) or 20 MHz (VDDE = 3.0–3.6 V) to meet the timing
specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification.
—tCYC
9
TCK duty cycle
tTDC
40
60
%
10
TDI, TMS data setup time
tNTDIS, tNTMSS
8—
ns
11
TDI, TMS data hold time
tNTDIH, tNTMSH
5—
ns
12
TCK low to TDO data valid
tJOV
VDDE = 2.25–3.0 V
0
12
ns
VDDE = 3.0–3.6 V
0
10
ns
13
RDY valid to MCKO 5
5 The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly.
——
—
1
2
3
4
5
MCKO
MDO
MSEO
EVTO
Output Data Valid
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