參數(shù)資料
型號(hào)： MPC5200BV400BR2
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 400 MHz, MICROPROCESSOR, PBGA272
封裝： 27 X 27 MM, 1.27 MM PITCH, HALIDE FREE, PLASTIC, BGA-272
文件頁(yè)數(shù)： 5/80頁(yè)
文件大小： 788K
代理商： MPC5200BV400BR2
Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 0.6
Freescale Semiconductor
13
The MPC5200B clock generation uses two phase locked loop (PLL) blocks.
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal
system clock. The system clock frequency is determined by the external reference frequency and
the settings of the SYS_PLL configuration.
The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300
core clock frequency is determined by the system clock frequency and the settings of the
CORE_PLL configuration.
3.2.1
System Oscillator Electrical Characteristics
3.2.2
RTC Oscillator Electrical Characteristics
3.2.3
System PLL Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
fsys_xtal
15.6
33.3
35.0
MHz
O1.1
Oscillator start-up time
tup_osc
—
10
ms
O1.2
Table 9. RTC Oscillator Electrical Characteristics
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
RTC_XTAL frequency
frtc_xtal
—
32.768
—
kHz
O2.1
Table 10. System PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
fsys_xtal
(1)
NOTES:
1
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
15.6
33.3
35.0
MHz
O3.1
SYS_XTAL cycle time
tsys_xtal
66.6
30.0
28.5
ns
O3.2
SYS_XTAL clock input jitter
tjitter
(2)
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is
rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry.
—
150
ps
O3.3
System VCO frequency
fVCOsys
(1)
250
533
800
MHz
O3.4
System PLL relock time
tlock
(3)
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
—
100
sO3.5
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參數(shù)描述
MPC5200CBV266 功能描述:微處理器 - MPU 266MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5200CBV400 功能描述:微處理器 - MPU 400MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5200CBV400B 制造商:Freescale Semiconductor 功能描述:
MPC5200CVR266 功能描述:微處理器 - MPU NO-PB IND’L 5200 266MHZ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5200CVR400 功能描述:微處理器 - MPU NO-PB IND’L 5200 400MHZ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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