參數(shù)資料
型號(hào)： MPC5125YVN200
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 200 MHz, MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324
文件頁(yè)數(shù)： 46/92頁(yè)
文件大?。?/td> 640K
代理商： MPC5125YVN200
MPC5125 Microcontroller Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
50
4.3.4
External Interrupts
The MPC5125 provides three different kinds of external interrupts:
IRQ interrupts
GPIO interrupts with simple interrupt capability (not available in power-down mode)
Wakeup interrupts
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge-triggered mode.
4.3.5
SDRAM (DDR)
The MPC5125 memory controller supports these types of DDR devices:
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR (1.8V I/O supply voltage)
SDR D-RAM
JEDEC standards define the minimum set of requirements for compliant memory devices:
JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006
JEDEC standard, Double Data Rate (DDR) SDRAM specification, JESD79E, May 2005
JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006
The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR:
Full drive strength
Half drive strength (intended for lighter loads or point-to-point environments)
The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in Section 4.1, “DC
tH_POR_CONF
Reset configuration hold time after assertion of PORESET.
1 cycle
A3.15
tHR_SR_DELAY
Time from falling edge of HRESET to falling edge of SRESET.
4 cycles
A3.16
tHRHOLD
Time HRESET must be held low before a qualified reset occurs.
4 cycles
A3.17
tSRHOLD
Time SRESET must be held low before a qualified reset occurs.
4 cycles
A3.18
tSRMIN
Time SRESET is asserted after it has been qualified.
1 cycles
A3.19
NOTES:
1 The timings will change when using the PLL lock detection circuit.
Table 20. IPIC Input AC Timing Specifications
Descriptions
Symbol
Min
Unit
Spec ID
IPIC inputs — minimum pulse width
tPICWID
2T
ns
A4.1
Table 19. Reset Timing (continued)
Symbol
Description
Value
(XTALI CLOCK)
SpecID
相關(guān)PDF資料
PDF描述
MPC5125YVN400 32-BIT, FLASH, 400 MHz, MICROCONTROLLER, PBGA324
MPC5200CVR400B 400 MHz, MICROPROCESSOR, PBGA272
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5125YVN400 功能描述:微處理器 - MPU POWERPC EMBEDDED SOC SOC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5125YVN400 制造商:Freescale Semiconductor 功能描述:ICMICROPROCESSOR32-BITCMOSPBGA324PI
MPC5125YVN400R 制造商:Freescale Semiconductor 功能描述:POWERPC EMBEDDED SOC - Tape and Reel
MPC5200 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications
MPC5200B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller
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