參數(shù)資料
型號(hào)： MPC5123YVY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù)： 15/86頁
文件大?。?/td> 1266K
代理商： MPC5123YVY400BR
MPC5121E/MPC5123 Data Sheet, Rev. 1
Electrical and Thermal Characteristics
Freescale Semiconductor
22
3.1.5
Power Dissipation
Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core
digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and
CORE_PLL_AVDD), the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the
PHYs (supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of
operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated
for each application case using the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f
is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the
MPC5121e/MPC5123 processor must not exceed the value, which would cause the maximum junction temperature to be
exceeded.
Eqn. 2
Table 9. Power Dissipation
Core Power Supply (VDD_CORE)
SpecID
Mode
High-Performance
Unit
e300 = 300 MHz, CSB = 200 MHz
Operational1,
1 Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 C.
NOTE
The maximum power depends on the supply voltage, process corner,
junction temperature, and the concrete application and clock
configurations.
The worst case power consumption could reach a maximum of 2000
mW.
800
mW
D5.1
Deep-Sleep1,
1mW
D5.2
Hibernation
20
uW
D5.3
PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Typical
25
mW
D5.4
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO)
Typical
300
mW
D5.5
PHY Power Supplies (USB_VDDA, SATA_VDDA)
Typical
200
mW
D5.6
P
IO
P
IOint
N
M
∑
+
CVDD_IO
2
f
×
=
P
total
P
core
P
analog
P
IO
PPHYs
++
+
=
Preliminary
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