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參數(shù)資料
| 型號： | MPC2510DTR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 87K |
| 代理商： | MPC2510DTR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MPC2510/D
1
REV 0
Motorola, Inc. 1998
11/98
Product Preview
Low Voltage PLL Clock Driver
The MPC2510 is a 3.3V compatible, PLL based zero delay buffer
targeted for high performance clock tree designs. With 11 outputs at
frequencies of up to 125MHz and output skews of 200ps the MPC2510 is
ideal for the most demanding clock tree designs. The device employs a
fully differential PLL design to minimize cycle–to–cycle and phase jitter.
The device is compliant to the 1.2 revision of the PC100 design
document.
Fully Integrated PLL
Output Frequency up to 125MHz in PLL Mode
Outputs Disable to a Logic Low
TQFP Packaging
50ps Cycle–to–Cycle Jitter
On Board Series Damping Resistors
The analog VCC pin of the device also serves as a PLL bypass select
pin. When driven low the AVCC pin will route the REF_CLK input around
the PLL directly to the outputs. The OE input is a logic enable for all of the
outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low
state.
The MPC2510 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50
transmission lines. The output impedance
of the MPC2510 is
40W with IV curves that are PC100 Rev 1.2
compliant. The device is packaged in a 24–lead TSSOP package to
provide the optimum combination of board density and performance.
Figure 1. Block Diagram
REF_CLK
FB_CLK
PLL
AVCC
Q0
Q9
QFB
OE
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
MPC2510
LOW VOLTAGE
PLL ZERO DELAY BUFFER
DT SUFFIX
24–LEAD TSSOP PACKAGE
CASE 948H–01
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