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參數(shù)資料
| 型號： | MP7542TD |
| 廠商： | MICRO POWER SYSTEMS |
| 元件分類： | DAC |
| 英文描述： | 5 V CMOS 4-Bit Input, 12-Bit Digital-to-Analog Converter |
| 中文描述： | PARALLEL, 4 BITS INPUT LOADING, 12-BIT DAC, CDIP16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 108K |
| 代理商： | MP7542TD |
MP7542
5
Rev. 2.00
Figure 1. Timing Diagram
t
AWS1
ADDRESS BUS VALID
DATA
BUS VALID
t
CWS1
t
AWH
t
CWH
t
AWS2
t
WR
t
CWS2
t
DS
t
DH
V
INH
V
INL
V
INH
V
INL
V
INH
V
INL
A0 - A1
CS
WR
DB3 - DB0
MP7542 Operation
MP7542 Control Inputs
A
1
A
0
CS
WR
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
1
Resets DAC 12-bit register to code 0000 0000 0000
No operation; device not selected
NOTES
1.
2.
3.
4.
5.
1 indicates logic HIGH
0 indicates logic LOW
X indicates don’t care
indicates LOW to HIGH transition
MSB XXXX XXXX XXXX LSB
high
byte
byte
6.
Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable.
Table 1. Truth Table
CLR
0
0
0
0
0
X
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Load LOW byte data register on edges as shown
Load MIDDLE byte data register on edges as shown
Load HIGH byte data register on edges as shown
Load 12-bit DAC register with data in LOW byte, MIDDLE
byte, & HIGH byte data registers
Load applicable
data register
with data at
D
0
- D
3
middle
low
byte
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