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參數(shù)資料
| 型號： | MP7529BJS |
| 廠商： | MICRO POWER SYSTEMS |
| 元件分類： | DAC |
| 英文描述： | 5 V CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.2 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 114K |
| 代理商： | MP7529BJS |
MP7529B
5
Rev. 2.00
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (Table 1.). When CS and WR
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
VALID
CS
DAC A/
DAC B
WR
NOTE:
1.
Figure 1. Write Cycle Timing Diagram
DB7-DB0
VALID
DAC A/
DAC B
CS
WR
DAC A
DAC B
L
H
X
X
L
L
H
X
H = High State
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
L = Low State
X = Don’t Care
Table 1. DAC’s Mode Selection
Timing measured from (V
IH
+ V
IL
) /2
t
CS
t
CH
t
AS
t
AH
t
WR
t
DS
t
DH
MICROPROCESSOR INTERFACE
DAC A
DAC B
DB0
DB7
ADDRESS
DECODE
LOGIC
A0-A15
φ
2
D0–D7
A+1***
A**
MP7529B*
CPU
6800
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
DAC A
DAC B
DB0
DB7
A8-A15
AD0–AD7
ADDRESS
DECODE
LOGIC
A+1***
A**
MP7529B*
CPU
8085
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
LATCH
8212
ALE
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
V
MA
Address Bus
Data Bus
Address Bus
ADDR/Data Bus
DAC A/DAC B
CS
WR
DAC A/DAC B
CS
WR
WR
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