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參數(shù)資料
| 型號(hào)： | MP7226LS |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | DAC |
| 英文描述： | BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO20 |
| 封裝： | 0.300 INCH, SOP-20 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大小： | 179K |
| 代理商： | MP7226LS |
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MP7226
8
Rev. 2.00
Figure 2. Simplified Output Buffer Amplifiers
V
DD
V
IN
AGND
V
SS
Output
The amplifiers outputs may be shorted to ground. However,
the power dissipation of the package should not exceed the
maximum limit.
Digital Inputs
All of the digital inputs to this DAC maintain TTL level inter-
face compatibility and can also be driven directly with 5V CMOS
logic inputs. The digital inputs are ESD protected to a rating of
2000 volts.
Digital Interface Logic
The MP7226 allows direct interface to most microprocessor
buses without additional interface circuitry.
Figure 3.shows the input control logic circuit diagram and
Table 1.shows the control logic truth table and operation for
WR, A1, A0. The address lines A0, and A1 determine which
DAC will accept the input data. The WR input determines
whether the selected DAC is transparent (output follows the in-
put), latched, or no operation. The WR input will also inhibit
power on reset of the DAC latches to 0, if its initial state = 0 after 5
μ
s of power.
Figure 4.shows the write cycle timing diagram. When the WR
signal is low, the input latch of the selected DAC is transparent,
and the DAC’s output corresponds to the value present on the
data bus. On some data buses, data is not always valid for the
entire period that the WR signal is low and can cause unwanted
data at the output. Ensuring that the write pulse (WR) conforms
to the data hold time, (t4) spec will prevent this problem.
Figure 3. Input Control Logic
WR
To DAC1 Latch Enable
To DAC2 Latch Enable
To DAC3 Latch Enable
To DAC4 Latch Enable
A0
A1
1 of 4
Decoder
H
L
L
L
L
X
L
L
L
H
H
X
L
L
H
L
H
WR
A1
A0
Operation
No Operation;
Device Not Selected
DAC 1 Transparent
DAC 1 Latched
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
Table 1. Truth Table
Figure 4. Write Cycle Timing Diagram
Address
Data
WR
t
AS
t
AH
t
WR
t
DS
t
DH
V
INH
V
INL
5 V
0 V
5 V
0 V
5 V
0 V
NOTE: When the WR signal is low, the input latch of the se-
lected DAC is transparent and any invalid data at this time will
cause erroneous output.
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