
MP7226
7
Rev. 2.00
D/A CONVERTER SECTION
The MP7226 contains four matched, 8-bit, voltage-mode Dig-
ital-to-Analog Converters (DACs) which incorporate an MPS
pioneered unique bit decoding technique. This decoding
scheme reduces the maximum binary weight carried by any re-
sistor switch, reducing the accuracy required of the switches
and resistor network.
In the MP7226, the first three MSBs are decoded into three
equal current sources, each contributing 25% of the full scale
output current.
Decoding two bits to three, a 1% change in any one of the
converter’s three decoded current sources affects the output by
no more than 0.25% of full scale, compared with 0.5% in a con-
ventional R-2R type CMOS DAC.
The output voltages have the same polarity as the reference
voltage, allowing single supply operation. The voltage refer-
ence range is from +2V to +10V. Each DAC uses a highly-stable,
thin-film, ladder network and high-speed NMOS switches.
Figure 1.shows a simplified circuit diagram for one channel.
2R
4R
4R
4R
4R
2R
2R
Switch Drivers
Figure 1. Simplified D/A Circuit Diagram
–
+
2 to 3 Decoder
4R
4R
V
REF
AGND
Shown for all 1s on DAC
V
OUT
V
REF
Input
The V
REF
and AGND are common to all four DACs and set
the full-scale output. The input impedance of the V
REF
pin is the
parallel combination of the four individual DAC reference imped-
ances and is code dependent. This impedance varies from 2k
to 500k
. Therefore, it is very important that the external refer-
ence source output impedance is low enough so that its output
voltage will not be affected by the varying digital code. Due to
transient currents at the V
REF
input during digital code changes,
a 0.1
μ
F or greater decoupling capacitor on that V
REF
input is
recommended. The input capacitance at the V
REF
pin is also
code dependent and typically varies from less than 120pF to
350pF.
Each V
OUT
voltage can be represented by a digitally pro-
grammable voltage source using the following expression :
V
OUT
= Dn X V
REF
/256
where Dn is the decimal equivalent to the digital input code
and can vary from 0 to 255.
Output Buffer Amp
Each D/A converter output is buffered by a unity gain nonin-
verting BiCMOS amplifier which has slew rate greater than 2 V/
μ
s . The output buffer settles to 1/2 LSB in less than 4
μ
s when
driving a load of 2k
in parallel with 100pF with a full scale transi-
tion from 0V to +10V or from +10V to 0V . The buffers can drive
2k
and 500pF to 10V levels without oscillation.
A simplified circuit diagram of the output buffer is shown in
Figure 2.The Input stage is provided by BiCMOS PNP transis-
tors with resulting lower input offset voltage, offset voltage drift
over time and noise when compared to MOS process . The am-
plifier output stage uses a substrate NPN bipolar device to pro-
vide a low output impedance, high-output current capability.
The MP7226 is specified for single or dual power supply op-
eration, with only the buffer amplifier outputs using V
SS
supply
current . Operating the MP7226 from dual supplies will improve
the negative going output settling time near ground. In dual sup-
ply voltage operation , the output amplifier can sink 500
μ
A when
V
OUT
= 0 V.