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參數(shù)資料
| 型號： | MP1232A |
| 廠商： | Exar Corporation |
| 英文描述： | CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter |
| 中文描述： | 微處理器的CMOS兼容雙緩沖12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 126K |
| 代理商： | MP1232A |
MP1230A/31A/32A
6
Rev. 2.00
THEORY OF OPERATION
Figure 1. Functional Diagram
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
Q
Q
Q
Q
D
D
D
D
Q
Q
Q
Q
MSB
LSB
8-Bit
Input
Latch
4-Bit
Input
Latch
12-Bit
DAC
Register
12-Bit
Multiplying
D/A
Converter
BYTE1/BYTE2
CS
WR1
XFER
WR2
DGND
AGND
LE
LE
LE
When LE = 1, Q Outputs Follow D Inputs
When LE = 0, Q Outputs are Latched
V
DD
V
REF
R
FB
I
OUT1
I
OUT2
DB11 (MSB) (DB3)
DB10 (DB2)
DB9 (DB1)
DB8 (DB0)
DB7
DB6
DB5
DB4
Digital Interface
Figure 1.shows the internal control logic that controls the
writing of the input latches. It is easy to understand how the
MP1230A/31A/32A works by understanding each basic opera-
tion.
Writing to Input Latches
The condition BYTE1/BYTE2= high, CS = WR1 = 0 loads the
data bus DB11-DB4 into both input latches.
A second cycle with BYTE1/BYTE2 = low (Figure 2.) loads
the pins DB11-DB8 (DB3-DB0) into the 4-bit input latch.
Timing diagrams show the inputs CS and DB11-DB0 to be
stable during the entire writing cycle. In reality all the above sig-
nals can change (Figure 2.) as long as they meet the timing con-
ditions specified in the Electrical Characteristic Table.
Figure 2. Write Cycles to Input Latches
WR1
CS
BYTE1/BYTE2
DATA
Transferring Data to the DAC Latches
Once one or all the input latches have been loaded, the condi-
tion XFER= WR2= low transfers the content of the input latches
in the DAC latch. The outputs of the DAC latch change and the
DAC current (I
OUT
) will reach a new stable value within the set-
tling time t
S
(Figure 3.).
WR2
XFER
DB11-0
t
S
Figure 3. Transfer Cycles from
Input Latches to DAC Latches
or
or
I
OUT
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