參數(shù)資料
型號: MP1231ABS
廠商: EXAR CORP
元件分類: DAC
英文描述: CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter
中文描述: PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝: 0.300 INCH, SOIC-20
文件頁數(shù): 1/12頁
文件大小: 126K
代理商: MP1231ABS
MP1230A/31A/32A
CMOS Microprocessor Compatible
Double-Buffered 12-Bit
Digital-to-Analog Converter
1
Rev. 2.00
FEATURES
Superior Ruggedized 1230 Series: 2 KV ESD
Four Quadrant Multiplication
Stable, More Accurate Segmented DAC Approach
0.2 ppm/
°
C Linearity Tempco
2 ppm/
°
C Max Gain Error Tempco
Lowest Sensitivity to Amplifier Offset
Lowest Output Capacitance (C
OUT
= 80pF)
Lower Glitch Energy
Monotonic over Temperature Range
Lower Data Bus Feedthrough @ CS = 1
V
DD
from +11 V to +16 V
Latch-Up Free CMOS Technology
12-Bit Bus Version: MP1208/1209/1210
16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements
for the 1230 series. The MP1230A series is manufactured using
advanced thin film resistors on a double metal CMOS process
which promotes significant improvements in reliability, latch-up
free performance and ESD protection.
The MP1230A series incorporates a unique decoding tech-
nique yielding lower glitch, higher speed and excellent accuracy
over temperature and time. 12-bit linearity is achieved without
trimming. Outstanding features include:
Stability: integral and differential linearity tempcos are rated
at 0.2 ppm/
°
C typical. Monotonicity is guaranteed over all
temperature ranges. Scale factor tempco is a low 2 ppm/
°
C
maximum.
Low Output Capacitance: Due to smaller MOSFET switch
geometries allowed by decoding, the output capacitance at
I
OUT1
and I
OUT2
is a low 80pF / 40pF and 25pF / 65 pF. This
less than half the competitive DAC 1230 series. Lower ca-
pacitance allows the MP1230A series to achieve settling
times faster than 1
μ
s for a 10 V step.
Low Sensitivity to Output Amplifier Offset: The linearity er-
ror caused by amplifier offset is reduced by a factor of 2 in the
MP1230A series over conventional R-2R DACs.
The MP1230A series uses a circuit which reduces transients
in the supplies caused by DATA bus transitions at CS
= 1.
SIMPLIFIED BLOCK DIAGRAM
DGND
12
D
Q
D
Q
DB11-DB4
DB3-DB0
BYTE1/BYTE2
D
Q
AGND
12
8
4
4
8
8
INPUT LATCH
DAC LATCH
V
DD
V
REF
R
FB
I
OUT1
I
OUT2
V
REF
CS
WR1
XFER WR2
LE
LE
LE
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