參數(shù)資料
型號(hào)： MN673794
廠商： PANASONIC CORP
元件分類： 消費(fèi)家電
英文描述： LSI FOR MPEG
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： 28 X 28 MM, PLASTIC, LQFP-208
文件頁(yè)數(shù)： 1/42頁(yè)
文件大?。?/td> 670K
代理商： MN673794
1. Overview
This IC is used to process a variety of items including the following ones: NTSC/PAL signal (Y/C and
composite video) I/O, 3D Y/C separation, TBC, DD conversion, frame sync, sync/clock generation, Rec
656 I/O.
Features
Analog input block
Composite video/Component Y input (10 bits at 27.0 MHz)
Component C input (10 bits at 27.0 MHz)
Analog control block
AGC (Auto Gain Control), clamp control, ACC (Auto Color Control)
Digital I/O block
Digital video I/O (ITU-R Rec 656: Y/Cr/Cb multiple, 8 bits at 27 MHz)
Digital video input clock must be synchronized with the system clock of 27 MHz.
Signal processing block
3D Y/C separation (image movement adaptive processing: NTSC), 2D Y/C separation (PAL)
TBC (Time Base Corrector) processing (velocity error correction/jitter correction)
Frame sync processing (See Note.)
NR processing (Y/C recursive NR)
Y/C separation is performed only in two dimensions (due to memory sharing) when the NR function is
in use.
Copyright VBLK detection
Macrovision (AGC pulse and color stripe) detection
VBID detection
Closed caption detection
WSS detection
Note: This IC uses a 27-MHz fixed clock. Therefore, input signals into the IC are not synchronized with
output signals from the IC. Therefore, a frame-skip or frame-hold occurs to standard and nonstandard
signals, the frequency of occurrence of which varies with the difference in frame frequency between
input signals and the 27-MHz fixed clock.
If the user does not want the occurrence of any frame-skip or frame-hold to standard signals,
externally generate 27-MHz clock pulses synchronized with the frames of the input signals, and input
the clock pulses into the IC.
A frame-skip refers to loss of the image in a single frame.
A frame-hold refers to the duplicated output of the image in the previous frame. *1
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