參數(shù)資料
型號(hào): MN63112S
廠商: PANASONIC CORP
元件分類: DRAM
英文描述: 2K-Bit EEPROM
中文描述: 256 X 8 3-WIRE SERIAL EEPROM, PDSO8
封裝: 0.225 INCH, PLASTIC, SOP-8
文件頁數(shù): 1/4頁
文件大?。?/td> 36K
代理商: MN63112S
1
EEPROMs
MN63112S
2K-Bit EEPROM
Overview
The MN63112S is a 2K-bit EEPROM supporting se-
rial I/O and operating on a single power supply with a
voltage between 1.8 and 5.5 V. It provides the following
pins for easy interfacing to microprocessors or
microcontrollers: chip select (CS), serial clock (SK), data
input (DI), and data output (DO). It includes a built-in
timer for use in automatically erasing and writing data
during data update operations.
The ORG pin provides a choice of two memory orga-
nizations: 256
×
8 bits when ORG is connected to ground
and 128
×
16 bits when ORG is connected to V
CC
. An
internal pull-up resistor makes the latter the default con-
figuration.
Conversion of peripheral circuits to CMOS realizes
great reductions in power consumption. Use of floating
gate memory cells and a built-in error correction circuit
ensures reliable operation for 10
5
write cycles.
Features
Choice of memory organizations: 256
×
8 bits and
128
×
16 bits
Floating gate memory cells
Function blocking erroneous writes
Low power consumption
- Reads: max. 6.6 mW for V
CC
= 3.3 V
- Standby: max. 66
μ
W for V
CC
= 3.3 V
Built-in self-timer for use in automatically erasing
and writing
Built-in error correction circuit that guarantees 10
5
write cycles
10-year data preservation period
Applications
Keyless entry systems, cordless telephones, storage for
recognition and adjustment data for terminals, etc.
Pin Assignment
SOP008-P-0225
( TOP VIEW )
1
2
3
4
CS
SK
DI
DO
8
7
6
5
V
CC
N.C.
ORG
GND
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