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參數(shù)資料
| 型號： | MN103SD0Q |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 60 MHz, MICROCONTROLLER, PBGA257 |
| 封裝： | 11 X 11 MM, LEAD FREE, PLASTIC, UBGA-257 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 374K |
| 代理商： | MN103SD0Q |
MAF00026EEM
MN103SD0 Series
Type
MN103SD0Q
MN103SFD0R
Internal ROM type
Mask ROM
FLASH
ROM (byte)
768K
1024K
RAM (byte)
32K
40K
Package (Lead-free)
UBGA257-P-1111A
Minimum Instruction
Execution Time
16.7 ns (at 2.7 V to 3.6 V, 60 MHz)
Interrupts
RESET. IRQ × 11. NMI. Key input. Timer × 32. Input capture × 16. PWM × 6. SIF × 24. I2C × 4. DMA × 18. WDT. A/D. System error
Timer Counter
8-bit timer × 8
Reload-down count. Cascade connection possible (usable as a 16-bit to 32-bit timer)
16-bit timer × 6
Up-down count. Input capture. PWM output. Compare/capture register 2 channnels
16-bit timer × 6
Reload-down count
Watchdog timer × 1
Serial interface
UART/Synchronous interface selective × 10: Serial 0, 1, 3 to A
Start-stop synchronization/Synchronization commonly used (16 bytes containing transmission/reception FIFO): Serial 2
I2C serial interface, multi master transmission/reception function × 2
DMA controller
Number of channels: 6 channels
Unit of transfer: 8/16/32 bits
Maximum transfer cycles: 65535
Starting factor: External interrupt. Timer. Input capture. PWM. Serial transmission/reception. I2C transmission/reception. A/D conversion
nish. Software
Transfer method: 2-bus cycle transfer
Adressing modes: Fixed. Increment. Decrement
Transfer mode: Word transfer. Burst transfer. Intermittent transfer
I/O Pins
I/O
194 : Common use
Input
1 : Exclusive
A/D converter
10-bit × 32 channels
PWM
12/14-bit resolution × 6 channels
ICR
28-bit × 13 channels + 16-bit × 6 channels (common with timer)
OCR
16-bit × 12 channels (common with timer)
Timer Synchronous Output
4-bit (synchronous output) × 2 channels
ROM Correction
8 channels
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