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參數(shù)資料
| 型號(hào)： | MN102H797 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大?。?/td> | 616K |
| 代理商： | MN102H797 |
MN102H797
RAM (
×××××8-bit)
ROM (
×××××8-bit)
Type
Package
LQFP064-P-1414 *Lead-free
Minimum Instruction
Execution Time
With main clock operated
83.3 ns (at 3.0 to 3.6 V, 12 MHz)
Interrupts
RST pin Watchdog Timer counter 0, 1 underflow Timer counter 2 under/overflow
Timer counters 2 to 4 compare capture A External 0 to 3 Serial ch.0 to 1 transmission
Serial ch.0 to 1 reception A/D conversion finish USB general-purpose USBSOF
Timer Counter
Timer counter 0: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; prescaler 0; TM0IO pin
Interrupt source Timer counter 0 underflow
Timer counter 1: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; prescaler 0; TM1IO pin
Interrupt source Timer counter 1 underflow
Connectable
Timer counters 0 to 1
Timer counter 2: 16-bit
× 1 (timer output, event count, input capture, PWM output, 2-phase encoder input)
Clock source SYSCLK; 1/8 of SYSCLK; timer counter 0 or 1 output; 2-phase encoding of
TM2IOA pin/TM2IOB pin (1
×, 4×) TM21OB pin
Interrupt source Timer counter 2 under/overflow; timer counter 2 compare capture A;
timer counter 2 compare capture B
Timer counter 3: 16-bit
× 1 (timer output, event count, input capture, PWM output, 2-phae encode input)
Clock source SYSCLK; 1/8 of SYSCLK; timer counter 0 or 1 output;
2-phase encoding TM3IOA pin/TM3IOB pin (1
×, 4×)
TM31OB pin
Interrupt source Timer counter 3 compare capture A
Timer counter 4: 16-bit
× 1 (timer output, event count, input capture, PWM output, 2-phae encode input)
Clock source SYSCLK; 1/8 of SYSCLK; timer counter 0 or 1 output;
2-phase encoding TM4IOA pin/TM4IOB pin (1
×, 4×)
TM41OB pin
Interrupt source Timer counter 4 compare capture A
16 K
MN102H797
1 K
USB Functions
Conforms to USB1.1.
USB transceiver built-in
Full-speed (12 Mbps) supported.
5 end points (FIFO built-in independently)
FIFO size
(EP0, 1, 2, 3, 4): 16, 64, 64, 64, 64 bytes
EP0
Control transfer
IN/OUT (two ways)
EP1 to EP4
Interrupt/Bulk/Isochronous transfer supported.
Settable to IN or OUT.
Double Buffering function supported.
When the MAXP size is set to a half or less of the MAXFIFO size for each EP, the Double Buffering function is
made valid automatically.
MAE00012CEM
176
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MN102H81G | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN102H81G |
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