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參數(shù)資料
| 型號(hào)： | MN101D10G |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MN101D10F |
| 中文描述： | 8-BIT, MROM, 14.32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 18 X 18 MM, LEAD FREE, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | MN101D10G |
MN101D10F, MN101D10G
OSD
Display mode
Applicable broadcasting system
Screen configuration
Character type
Character size
Enlarged characters
Character interpolation
Line background color
Line background intensity
Screen background color :
Character color
Character intensity
Border function
Border brightness
Blinking
Inverted character
Halftone
Input
Clamp method
Output
Measure against image fluctuation
Dot clock
MESECAM compatibility
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menu(intermal synchronized) display, superimpose(externally synchronized) display
NTSC, PAL, PAL-M, PAL-N
24 characters
×
2n rows (n = 1 to 6)
max. 256 character types (variable, include special characters)
12
×
18 dots (vertical direction: 1 dot for 2H at not enlargement)
each
×
2 settings in horizontal and vertical
none
8-hue settable in the row unit at menu display
8 gradations settable in the row unit
8-huesettable at menu display
white
8 gradations settable in the row unit
1-dot border in 8 directions
4 gradations settable in the row unit
none (covered by software)
settable in the character unit
none
composite video signal input (output level: 1 V[p-p] / 2 V[p-p])
sync tip clamp, clamp level in 4 levels
composite video output
built-in AFC circuit
1/2 of OSC oscillation clock (automatic phase adjustment)
Subcarrier leak function for superimpose display
See the next page for electrical characteristics, pin assignment and support tool.
MAD00043BEM
XDS
Built-in U.S. closed caption data slicer (optional 1 line data can be extracted.)
ROM Correction
Correcting address designation: up to 3 addresses possible
Correction method: correction program being saved in internal RAM
I/O Pins
76
Common use: 56
I/O
1
Common use: 1
Input
A/D Inputs
8-bit
×
12-ch. (without S/H)
PWM
13-bit
×
2-ch. (at repetition cycle 572
μ
s at 14.32 MHz),
8-bit
×
1-ch. (at repetition cycle 35.7
μ
s, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz)
16-bit
×
2-ch.(Speed system),
18-bit
×
4-ch.(Phase system)
16-bit
×
3 (Synchronous output
×
2, Rec CTL
×
1 )
ICR
OCR
Special Ports
3-state output (PTO) VLP pin; CTL input;Capstan FG input; Cylinder(Drum) PG/FG inputs; HSW output;
Head amp/ Rotary outputs; built-in FG amp; output of 1/4 OSC oscillation clock (1 V[p-p])
Notes
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