參數(shù)資料
型號: MN101D06F
廠商: PANASONIC CORP
元件分類: 微控制器/微處理器
英文描述: RESET
中文描述: 8-BIT, MROM, 14.32 MHz, MICROCONTROLLER, PQFP100
封裝: 18 X 18 MM, LEAD FREE, PLASTIC, QFP-100
文件頁數(shù): 1/5頁
文件大?。?/td> 118K
代理商: MN101D06F
RAM (
×
8-bit)
Package
ROM (
×
8-bit)
Type
QFP100-P-1818B
*Lead-free
MN101D06F , MN101D06G , MN101D06H
Minimum Instruction
Execution Time
With main clock operated
0.1397
μ
s (at 4.0 V to 5.5 V, 14.32 MHz)
71.5
μ
s (at 3.0 V to 5.5 V fixed to 14.32 MHz internal frequency division)
61
μ
s (at 2.2 V to 5.5 V, 32.768 kHz)
When sub-clock operated
Interrupts
RESET Runaway External 0 External 1 External 2 External 3 External 4 key input (P50 to 54)
Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 6 Capstan FG Control HSW
Cylinder(Drum) FG Servo V-sync Synchronous output OSD XDS Serial 0 Serial 1 Serial 2
A/D (common with PWM 4 reference frequency) OSD V-sync
Timer counter 0: 16-bit
×
1
(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])
Clock source····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overflow of timer counter 6;
1/512 of XI oscillation clock or OSC oscillation clock frequency
Interrupt source ················ overflow of timer counter 0
Timer Counter
Timer counter 1: 16-bit
×
1 (timer function, linear timer counter function)
Clock source····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal
Interrupt source ················ overflow of timer counter 1
Timer counter 2: 16-bit
×
1 (timer function, input capture, duty judgment of CTL signal(VISS/VASS detection function))
Clock source····················· 1/2, (1/4,) 1/8, (1/16,) 1/12, (1/24) of system clock frequency
Interrupt source················ overflow of timer counter 2; input of CTL specified edge; underflow of timer 2
shift register 4-bit counter; coincidence of timer 2 shift register with timer 2
shift register compare register
Timer counter 3: 16-bit
×
1
(timer function, detection of serial indexing, generation of remote control output carrier frequency)
Clock source····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; XI oscillation clock
Interrupt source ················ overflow of timer counter 3
Timer counter 4: 16-bit
×
1 (timer function, event count [P15 input], generation of serial transmission clock)
Clock source····················· 1/8, (1/16) of system clock frequency; external clock input
Interrupt source ················ overflow of timer counter 4; coincidence of timer counter 4 with OCR4
Timer counter 5: 19-bit
×
1 (watchdog, stable oscillation waiting function)
Clock source ····················· system clock
Watchdog interrupt source ··
1/2
16
, 1/2
19
of timer counter 5 frequency
Clear by stable oscillation ··
after 256 counts by timer counter 5 (2
18
counts of OSC oscillation clock)
Timer counter 6: 16-bit
×
1 (clock function [max. 2 s])
Clock source ····················· 1/512 of OSC oscillation clock frequency; XI oscillation clock;
1/4, (1/8,) 1/64, (1/128) of system clock frequency
Interrupt source ················ 1/2
13
, 1/2
14
, 1/2
15
overflow of timer counter 6
Timer counter 7: 8-bit
×
1 or 4-bit
×
2 (timer function, event count)
Clock source····················· 1/4, (1/8,) 1/16, (1/32) of system clock frequency; external clock input
Interrupt source················ overflow of timer counter 7 (although when 4-bit
×
2, there is one interrupt vector. )
Serial Interface
Serial 0: 8-bit
×
1 (synchronous type/start-stop synchronous type) (transfer direction of MSB/LSB selectable)
Synchronous type clock source
1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;
2-division timer 4 output; NSBT0 pin input
Clock for UART ·············· 8-division of above clock; 2-division timer 4 output; NSBT0 pin input
96 K
MN101D06F
3 K
128 K
MN101D06G
4 K
160 K
MN101D06H
5 K
MAD00029FEM
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