參數(shù)資料
型號(hào)： MMJL-29C80FHXXX
廠商： ATMEL CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQCC44
封裝： MQFP-44
文件頁(yè)數(shù)： 13/18頁(yè)
文件大小： 287K
代理商： MMJL-29C80FHXXX
29C80F
Rev. D (25 Mar.97)
68
MATRA MHS
other type of block must be placed in cycle
“191”.
ZZ :
ZZ input defines the block scanning to be
used (cf figure 1) for the input or the output
of coefficients, according to the CCITT
H261 requirements. ZZ signal is sampled
on the falling edge of CLK during the
BKLIN period (cf BLKIN definition).
PIX :
This input allows to choose input/output
pixel format, 9 bit 2’s complement format
(PIX=VIL) or 8 bit 2’s complement format
(PIX = VIH). The chosen format is
sampled by the falling edge of CLK during
the BKLIN period (cf BLKIN definition).
The JPEG 8 bit mode can be obtained by
inverting MSB on pixel data (bias +128).
Figure 1. Function of Synchronous Controls.
Control
State
Function
BLKIN
VIL
VIH
No action.
Block input synchronisation
BLKOUT
VOL
VOH
No action.
Block output synchronisation.
F/I
VIL
VIH
(valid during ”BLKIN period”)
Inverse DCT.
Forward DCT.
ZZ
VIL
VIH
(valid during ”BLKIN period”)
Normal scanning for coefficient block.
Zig–Zag scanning for coefficient block.
PIX
VIL
VIH
(valid during ”BLKIN period”)
9 bit 2’s complement pixel format.
8 bit 2’s complement pixel format.
Synchronous data
DI[..]
: Data Input Port
pin 8 to 11 and 14 to 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DO[..]
: Data Output Port
pin 38 to 35 and 32 to 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DI[..] : The data input port is sampled on falling edge of CLK.
Figure 2. 9 bit 2’s Complement Pixel Format for FDCT.
* FDCT :
The input data, for FDCT, is a 9 (8)-bit 2’s complement number (pixel) in the range –256, 257 (–128, 127).
Pin
DI11
DI10
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Weight
– 256
128
64
32
16
8
4
2
1
–
Digital value
– 28
27
26
25
24
23
22
21
20
(*)
(*) Must be fixed to VIL
Figure 3. 8 bit 2’s Complement Pixel Format for FDCT.
Pin
DI11
DI10
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Weight
– 128
65
32
16
8
4
2
1
–
Digital value
– 27
26
25
24
23
22
21
20
(*)
(*) Must be fixed to VIL
相關(guān)PDF資料
PDF描述
MMJL-29C80F 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQFP44
MMJL-29C80F/883 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQCC44
MMJL-29C80F/883 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQFP44
SMJL-29C80FHXXX 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQFP44
SMJL-29C80F/883 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQCC44
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