參數(shù)資料
型號(hào)： MMJL-29C80F/883
廠商： TEMIC SEMICONDUCTORS
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQFP44
封裝： MQFP-44
文件頁數(shù)： 15/18頁
文件大?。?/td> 287K
代理商： MMJL-29C80F/883
29C80F
Rev. D (25 Mar.97)
70
MATRA MHS
The 29C80F processes data blocks including 64 samples
and representing an 8
× 8 pixel or coefficient matrix. The
input blocks can be scanned :
–
line by line or column by column for pixels
–
line by line, column by column or in zig-zag mode (cf
H261) for coefficients.
Figure 8 shows the relation between input blocks
scanning order and output blocks scanning order.
Figure 8. 29C80F – Scanning Order.
Pixel/Coefficient Order
Coefficient/Pixel Order
01 09 17 25 33 41 49 57
01 02 03 04 05 06 07 08
02 10 18 26 34 42 50 58
09 10 11 12 13 14 15 16
03 11 19 27 35 43 51 59
17 18 19 20 21 22 23 24
Nl M d
04 12 20 28 36 44 52 60
<>
25 26 27 28 29 30 31 32
Normal Mode
05 13 21 29 37 45 53 61
<=>
33 34 35 36 37 38 39 40
06 14 22 30 38 46 54 62
41 42 43 44 45 46 47 48
07 15 23 31 39 47 55 63
49 50 51 52 53 54 55 56
08 16 24 32 40 48 56 64
57 58 59 60 61 62 63 64
Pixel Order
Coefficient Order
01 02 03 04 05 06 07 08
01 03 04 10 11 21 22 36
09 10 11 12 13 14 15 16
02 05 09 12 20 23 35 37
17 18 19 20 21 22 23 24
06 08 13 19 24 34 38 49
25 26 27 28 29 30 31 32
<>
07 14 18 25 33 39 48 50
33 34 35 36 37 38 39 40
<=>
15 17 26 32 40 47 51 58
41 42 43 44 45 46 47 48
16 27 31 41 46 52 57 59
49 50 51 52 53 54 55 56
28 30 42 45 53 56 60 63
Zi Z
M d
57 58 59 60 61 62 63 64
29 43 44 54 55 61 62 64
Zig-Zag Mode
01 09 17 25 33 41 49 57
01 02 06 07 15 16 28 29
02 10 18 26 34 42 50 58
03 05 08 14 17 27 30 43
03 11 19 27 35 43 51 59
04 09 13 18 26 31 42 44
04 12 20 28 36 44 52 60
<>
10 12 19 25 32 41 45 54
05 13 21 29 37 45 53 61
<=>
11 20 24 33 40 46 53 55
06 14 22 30 38 46 54 62
21 23 34 39 47 52 56 61
07 15 23 31 39 47 55 63
22 35 38 48 51 57 60 62
08 16 24 32 40 48 56 64
36 37 49 50 58 59 63 64
The 29C80F has synchronous input and output interfaces.
The input data (DI[..]) and input commands (BLKIN, F/I,
PIX, ZZ & /CLKEN) are sampled on the falling edge of
CLK. The rising edge of CLK drives the output latches
which provide computed data (DO[..]) and output control
(BLKOUT). An asynchronous command (/OEN) puts the
output latched buffers in high impedance.
BLKIN command must be activated one clock cycle
before the first data of the input block. All input
commands are taken into account on the falling edge of
the CLK period defined by BLKIN. In accordance with
the pipelined architecture, the 29C80F provides the
output control signal BLKOUT one clock cycle before
the first data of the output block.
A clock disable mode (/CLKEN) allows to stop internal
clocks. This command can be used to reduce the power
consumption or to adapt the flow rate (input/output
data - gap cycles -...).
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