
Electrical Specifications
OnCE, JTAG, and Boundary Scan Timing
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA
Electrical Specifications
605
22.14 OnCE, JTAG, and Boundary Scan Timing
Figure 22-9. Test Clock Input Timing
Table 22-14. OnCE, JTAG, and Boundary Scan Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)
No.
Characteristics
Symbol
Min
Max
Unit
1
TCLK frequency of operation
fJCYC
dc
1/2 x fsys
MHz
2
TCLK cycle period
tJCYC
2
—
tcyc
3
TCLK clock pulse width
tJCW
25
—
ns
4
TCLK rise and fall times
tJCRF
03
ns
5
Boundary scan input data setup time to TCLK rise
tBSDST
5
—
ns
6
Boundary scan input data hold time after TCLK rise
tBSDHT
24
—
ns
7
TCLK low-to-boundary scan output data valid
tBSDV
040
ns
8
TCLK low-to-boundary scan output high Z
tBSDZ
040
ns
9
TMS, TDI, and DE input data setup time to TCLK rise(1)
tTAPDST
7
—
ns
10
TMS, TDI, and DE input data hold time after TCLK rise
(1)
tTAPDHT
15
—
ns
11
TCLK low to TDO data valid
tTDODV
025
ns
12
TCLK low to TDO high Z
tTDODZ
09
ns
13
TRST assert time
tTRSTAT
100
—
ns
14
TRST setup time (negation) to TCLK high
tTRSTST
10
—
ns
15
DE input data setup time to CLKOUT rise
(1)
tDEDST
10
—
ns
16
DE input data hold time after CLKOUT rise
(1)
tDEDHT
2
—
ns
17
CLKOUT high to DE data valid
tDEDV
020
ns
18
CLKOUT high to DE high Z
tDEDZ
010
ns
1. Parameters 9 and 10 apply to the DE pin when used to enable OnCE. Parameters 15 and 16 apply to the DE pin when
used to request the processor to enter debug mode.
TCLK INPUT
VIL
VIH
44
2
3
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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