
Serial Peripheral Interface Module (SPI)
Functional Description
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA
Serial Peripheral Interface Module (SPI)
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391
Figure 17-12. SPI Clock Format 0 (CPHA = 0)
When CPHA = 0, the slave SS pin must be negated and reasserted
between bytes.
NOTE:
Clock skew between the master and slave can cause data to be lost
when:
CPHA = 0, and,
The baud rate is the SPI clock divided by two, and
The master SCK frequency is half the slave SPI clock frequency,
and
Software writes to the slave SPIDR just before the synchronized
SS signal goes low.
t
L
BEGIN TRANSMISSION
END TRANSMISSION
SCK (CPOL = 0)
SAMPLE INPUT
MOSI/MISO
CHANGE OUTPUT
MOSI PIN
SS PIN OUTPUT
MASTER ONLY
SCK (CPOL = 1)
MSB FIRST (LSBFE = 0):
LSB FIRST (LSBFE = 1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE OUTPUT
MISO PIN
SLAVE SS PIN
t
T
I
FOR t
T
, t
L
, t
l
MINIMUM 1/2 SCK
t
I
t
L
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transmissions (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for master mode and required for slave mode.
Legend:
F
Freescale Semiconductor, Inc.
n
.