
Functional Description and Application Information
Port Integration Module (9S12I32PIMV1)
MM912F634
Freescale Semiconductor
172
4.27.3.9
PIM Reserved Registers
4.27.3.10
Port A Input Register (PTIA)
4.27.3.11
PIM Reserved Register
Table 231. PIM Reserved Registers
Address 0x0008-0x0019
76
543
210
R
0
W
Reset
0
000
00
Note:
165. Read: Anytime.
Write: Unimplemented. Writing to these registers has no effect.
Table 232. Port A Input Register (PTIA)
Address 0x0120
76
543
210
R
0
PTIA5
PTIA4
PTIA3
PTIA2
PTIA1
PTIA0
W
u
uuu
uu
Note:
166. Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.
167. u = Unaffected by reset
Table 233. PTIA Register Field Descriptions
Field
Description
5-0
PTIA
Port A input data—
This register always reads back the buffered and synchronized state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
Table 234. PIM Reserved Register
Address 0x0121
76
543
210
R
0
W
Reset
0
000
00
Note:
168. Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.