參數(shù)資料
型號(hào): MM74HC594NX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 計(jì)數(shù)移位寄存器
英文描述: SERIAL IN PARALLEL OUT SHIFT REGISTER, PDIP16
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-16
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 58K
代理商: MM74HC594NX
January 1992
Revised May 1999
MM74HC594
8-Bi
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1999 Fairchild Semiconductor Corporation
DS010915.prf
www.fairchildsemi.com
MM74HC594
8-Bit Shift Register with Output Registers
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. Separate
clocks and direct overriding clears are provided for both the
shift register and the storage register. The shift register has
a direct-overriding clear, serial input, and serial output
(standard) pins for cascading. Both the shift register and
storage register use positive-edge triggered clocks. If both
clocks are connected together, the shift register state will
always be one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Low quiescent current: 80
A maximum
s Low input current: 1
A maximum
s 8-bit serial-in, parallel-out shift register with storage
s Wide operating voltage range: 2V to 6V
s Cascadable
s Shift register has direct clear
s Guaranteed shift frequency: DC to30 MHz
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Order Number
Package Number
Package Description
MM74HC594M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
MM74HC594N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
RCK
SCK
SCLR RCLR
Function
X
L
Storage Register cleared
XX
L
X
Shift Register cleared
Q’H = 0
X
HH
Shift Register clocked
QN = Qn1, Q0 = SER
XH
H
Contents of Shift
Register transferred
to output latches
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