VCC 5V, T
參數(shù)資料
型號: MM74HC574WMX
廠商: Fairchild Semiconductor
文件頁數(shù): 3/8頁
文件大?。?/td> 0K
描述: IC FLIP FLOP OCT D 3ST 20-SOIC
標準包裝: 1
系列: 74HC
功能: 標準
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 8
頻率 - 時鐘: 35MHz
延遲時間 - 傳輸: 18ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 7.8mA,7.8mA
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 標準包裝
其它名稱: MM74HC574WMXDKR
3
www.fairchildsemi.com
MM74HC574
AC Electrical Characteristics
VCC
5V, TA 25qC, tr tf 6 ns
AC Electrical Characteristics
VCC
2.0
6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating Frequency
60
33
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
CL 45 pF
17
27
ns
tPZH, tPZL
Maximum Output Enable Time
RL 1 k:
19
28
ns
CL 45 pF
tPHZ, tPLZ
Maximum Output Disable Time
RL 1 k:
14
25
ns
CL 5 pF
tS
Minimum Setup Time, Data to Clock
10
12
ns
tH
Minimum Hold Time, Clock to Data
35ns
tW
Minimum Pulse Clock Width
8
15
ns
Symbol
Parameter
Conditions
VCC
TA 25qCTA 40 to 85qCTA 55 to 125qC
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating Frequency
CL 50 pF
2.0V
33
28
23
MHz
4.5V
30
24
20
6.0V
35
28
23
tPHL, tPLH
Maximum Propagation
CL 50 pF
2.0V
18
30
38
45
ns
Delay, Clock to Q
CL 150 pF
2.0V
51
155
194
233
CL 50 pF
4.5V
13
23
29
35
ns
CL 150 pF
4.5V
19
31
47
CL 50 pF
6.0V
12
20
25
30
ns
CL 150 pF
6.0V
18
27
34
41
tPZH, tPZL
Maximum Output Enable
RL 1 k:
Time
CL 50 pF
2.0V
22
30
38
45
ns
CL 150 pF
2.0V
59
180
225
270
CL 50 pF
4.5V
14
28
35
42
ns
CL 150 pF
4.5V
20
36
45
54
CL 50 pF
6.0V
12
24
30
36
ns
CL 150 pF
6.0V
18
31
39
47
tPHZ, tPLZ
Maximum Output Disable Time
RL 1 k:
2.0V
15
30
38
45
ns
CL 50 pF
4.5V
12
25
31
38
6.0V
10
21
27
32
tS
Minimum Setup Time
2.0V
6
12
15
18
ns
Data to Clock
4.5V
20
25
30
6.0V
17
21
25
tH
Minimum Hold Time
2.0V
15
6
8
ns
Clock to Data
4.5V
0
6.0V
0
tTHL, tTLH
Maximum Output Rise
CL 50 pF
2.0V
6
12
15
18
ns
and Fall Time
4.5V
7
12
15
18
6.0V
6
10
13
15
tW
Minimum Clock Pulse Width
2.0V
30
15
20
24
ns
4.5V
9
16
20
24
6.0V
8
14
18
20
tr,tf
Maximum Clock Input Rise
2.0V
1000
ns
and Fall Time
4.5V
500
6.0V
400
CPD
Power Dissipation Capacitance
OC
VCC
5
pF
(Note 5) (per latch)
OC
GND
58
CIN
Maximum Input Capacitance
5
10
pF
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