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參數(shù)資料
| 型號(hào)： | MM74HC4046MX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | PHASE LOCKED LOOP, 7 MHz, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大小： | 250K |
| 代理商： | MM74HC4046MX |
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4
M
AC Electrical Characteristics
V
CC
= 2.0 to 6.0V, C
L
= 50 pF, t
r
= t
r
= 6 ns (unless otherwise specified.)
Symbol
Parameters
Conditions
V
CC
T
A
=
25C
Typ
25
T
A
=
40 to 85
°
C T
A
=
55 to 125
°
C
Guaranteed Limits
150
Units
AC Coupled
C (series)
=
100 pF
f
IN
=
500 kHz
2.0V
100
200
mV
Input Sensitivity,
Signal In
Maximum Output
4.5V
6.0V
2.0V
50
135
30
150
250
75
200
300
95
250
350
110
mV
mV
ns
t
r
, t
f
Rise and Fall Time
4.5V
6.0V
7
9
8
15
12
19
15
22
19
ns
ns
pF
C
IN
Phase Comparator I
t
PHL
, t
PLH
Maximum
Maximum Input Capacitance
2.0V
4.5V
65
25
200
40
250
50
300
60
ns
ns
Propagation Delay
6.0V
20
34
43
51
ns
Phase Comparator II
t
PZL
Maximum 3-STATE
2.0V
75
225
280
340
ns
Enable Time
4.5V
6.0V
2.0V
25
22
88
45
38
240
56
48
300
68
57
360
ns
ns
ns
t
PZH
, t
PHZ
Maximum 3-STATE
Enable Time
4.5V
6.0V
2.0V
30
25
90
48
41
240
60
51
300
72
61
360
ns
ns
ns
t
PLZ
Maximum 3-STATE
Disable Time
4.5V
6.0V
2.0V
32
28
100
48
41
250
60
51
310
72
61
380
ns
ns
ns
t
PHL
, t
PLH
Maximum
Propagation Delay
HIGH-to-LOW to Phase Pulses
Phase Comparator III
t
PHL
, t
PLH
Maximum
Propagation Delay
4.5V
6.0V
34
27
50
43
63
53
75
64
ns
ns
2.0V
4.5V
6.0V
75
25
22
200
40
34
250
50
43
300
60
51
ns
ns
ns
C
PD
Maximum Power
Dissipation Capacitance
All Comparators
V
IN
=
V
CC
and GND
130
pF
Voltage Controlled Oscillator (Specified to operate from V
CC
=
3.0V to 6.0V)
f
MAX
Maximum
Operating
C1
=
50 pF
R1
=
100
R2
=
∞
VCO
in
=
V
CC
C1
=
0 pF
R1
=
100
VCO
in
=
V
CC
4.5V
7
4.5
MHz
Frequency
6.0V
11
7
MHz
4.5V
12
MHz
6.0
14
MHz
Duty Cycle
50
%
Demodulator Output
Offset Voltage
VCO
in
–
V
dem
Offset
Variation
R
s
=
20 k
4.5V
0.75
1.3
1.5
1.6
V
R
s
=
20 k
VCO
in
=
1.75V
2.25V
4.5V
0.65
0.1
V
2.75V
0.75
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| MM74HC4046MTC | CMOS Phase Lock Loop |
| MM74HC4046SJ | CMOS Phase Lock Loop |
| MM74HC4046 | CMOS Phase Lock Loop |
| MM74HC4046M | CMOS Phase Lock Loop |
| MM74HC4046N | CMOS Phase Lock Loop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HC4046N | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lkd Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MM74HC4046N | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74HC CMOS 74HC4046 DIP16 6V |
| MM74HC4046N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
| MM74HC4046N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
| MM74HC4046NX | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:CMOS Phase Lock Loop |
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