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參數(shù)資料
| 型號： | MM74HC4046 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | 的CMOS鎖相環(huán) |
| 文件頁數(shù)： | 9/17頁 |
| 文件大小： | 250K |
| 代理商： | MM74HC4046 |
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www.fairchildsemi.com
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Detailed Circuit Description
(Continued)
FIGURE 2. Logic Diagram for VCO
The input to the VCO is a very high impedance CMOS
input and so it will not load down the loop filter, easing the
filters design. In order to make signals at the VCO input
accessible without degrading the loop performance a
source follower transistor is provided. This transistor can
be used by connecting a resistor to ground and its drain
output will follow the VCO input signal.
An inhibit signal is provided to allow disabling of the VCO
and the source follower. This is useful if the internal VCO is
not being used. A logic high on inhibit disables the VCO
and source follower.
The output of the VCO is a standard high speed CMOS
output with an equivalent LSTTL fanout of 10. The VCO
output is approximately a square wave. This output can
either directly feed the comparator input of the phase com-
parators or feed external prescalers (counters) to enable
frequency synthesis.
PHASE COMPARATORS
All three phase comparators share two inputs, Signal In
and Comparator In. The Signal In has a special DC bias
network that enables AC coupling of input signals. If the
signals are not AC coupled then this input requires logic
levels the same as standard 74HC. The Comparator input
is a standard digital input. Both input structures are shown
in Figure 3.
The outputs of these comparators are essentially standard
74HC voltage outputs. (Comparator II is 3-STATE.)
FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM74HC4046M | CMOS Phase Lock Loop |
| MM74HC4046N | CMOS Phase Lock Loop |
| MM74HC4046NX | CMOS Phase Lock Loop |
| MM74HC4049MTCX | Hex Inverting Logic Level Down Converter . Hex Logic Level Down Converter |
| MM74HC4049MX | Hex Inverting Logic Level Down Converter . Hex Logic Level Down Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HC4046J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
| MM74HC4046J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
| MM74HC4046M | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lkd Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MM74HC4046M | 制造商:Fairchild Semiconductor Corporation 功能描述:IC PLL LOGIC ROHS COMPLIANT:NO |
| MM74HC4046M | 制造商:Fairchild Semiconductor Corporation 功能描述:74HC CMOS SMD 74HC4046 SOIC16 |
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