VCC 2.0 6.0V, C
參數(shù)資料
型號(hào): MM74HC374WM
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 0K
描述: IC FLIP FLOP OCTAL D 3ST 20SOICW
標(biāo)準(zhǔn)包裝: 36
系列: 74HC
功能: 標(biāo)準(zhǔn)
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
頻率 - 時(shí)鐘: 35MHz
延遲時(shí)間 - 傳輸: 20ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 7.8mA,7.8mA
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1209 (CN2011-ZH PDF)
www.fairchildsemi.com
4
MM
74HC374
AC Electrical Characteristics
VCC
2.0
6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC
2f I
CC VCC, and the no load dynamic current consumption,
IS CPD VCC f ICC.
Symbol
Parameter
Conditions
VCC
TA 25qCTA 40 to 85qCTA 55 to 125qC
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
CL 50 pF
2.0V
6
5
4
MHz
Frequency
4.5V
30
24
20
MHz
6.0V
35
28
23
MHz
tPHL, tPLH Maximum Propagation
CL 50 pF
2.0V
68
180
225
270
ns
Delay, Clock to Q
CL 150 pF
2.0V
110
230
288
345
ns
CL 50 pF
4.5V
22
36
45
48
ns
CL 150 pF
4.5V
30
46
57
69
ns
CL 50 pF
6.0V
20
31
39
46
ns
CL 150 pF
6.0V
28
40
50
60
ns
tPZH, tPZL Maximum Output
RL 1 k:
Enable Time
CL 50 pF
2.0V
50
150
189
225
ns
CL 150 pF
2.0V
80
200
250
300
ns
CL 50 pF
4.5V
21
30
37
45
ns
CL 150 pF
4.5V
30
40
50
60
ns
CL 50 pF
6.0V
19
26
31
39
ns
CL 150 pF
6.0V
26
35
44
53
ns
tPHZ, tPLZ Maximum Output
RL 1 k:
2.0V
50
150
189
225
ns
Disable Time
CL 50 pF
4.5V
21
30
37
45
ns
6.0V
19
26
31
39
ns
tS
Minimum Setup Time
2.0V
50
60
75
ns
4.5V
9
13
15
ns
6.0V
9
11
13
ns
tH
Minimum Hold Time
2.0V
5
30
5
ns
4.5V
5
ns
6.0V
5
ns
tW
Minimum Pulse Width
2.0V
30
80
100
120
ns
4.5V
9
16
20
24
ns
6.0V
8
14
18
20
ns
tTHL, tTLH Maximum Output Rise
CL 50 pF
2.0V
25
60
75
90
ns
and Fall Time
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
tr, tf
Maximum Input Rise and
2.0V
1000
ns
Fall Time, Clock
4.5V
500
ns
6.0V
400
ns
CPD
Power Dissipation
(per flip-flop)
Capacitance (Note 5)
OC
VCC
30
pF
OC
GND
50
pF
CIN
Maximum Input Capacitance
5
10
pF
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