VCC 5V, T
參數(shù)資料
型號(hào): MM74HC373MTCX
廠(chǎng)商: Fairchild Semiconductor
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 0K
描述: IC LATCH OCTAL D 3ST 20TSSOP
標(biāo)準(zhǔn)包裝: 1
系列: 74HC
邏輯類(lèi)型: D 型透明鎖存器
電路: 8:8
輸出類(lèi)型: 三態(tài)
電源電壓: 2 V ~ 6 V
獨(dú)立電路: 1
延遲時(shí)間 - 傳輸: 19ns
輸出電流高,低: 7.8mA,7.8mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1209 (CN2011-ZH PDF)
其它名稱(chēng): MM74HC373MTCXDKR
3
www.fairchildsemi.com
MM74HC373
AC Electrical Characteristics
VCC
5V, TA 25qC, tr tf 6 ns
AC Electrical Characteristics
VCC
2.0
6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
tPHL, tPLH
Maximum Propagation Delay, Data to Q CL 45 pF
18
25
ns
tPHL, tPLH
Maximum Propagation Delay, LE to Q
CL 45 pF
21
30
ns
tPZH, tPZL
Maximum Output Enable Time
RL 1 k:
20
28
ns
CL 45 pF
tPHZ, tPLZ
Maximum Output Disable Time
RL 1 k:
18
25
ns
CL 5 pF
tS
Minimum Set Up Time
5ns
tH
Minimum Hold Time
10
ns
tW
Minimum Pulse Width
9
16
ns
Symbol
Parameter
Conditions
VCC
TA 25qCTA 40 to 85qCTA 55 to 125qC
Units
Typ
Guaranteed Limits
tPHL, tPLH Maximum Propagation
CL 50 pF
2.0V
50
150
188
225
ns
Delay, Data to Q
CL 150 pF
2.0V
80
200
250
300
ns
CL 50 pF
4.5V
22
30
37
45
ns
CL 150 pF
4.5V
30
40
50
60
ns
CL 50 pF
6.0V
19
26
31
39
ns
CL 150 pF
6.0V
26
35
44
53
ns
tPHL, tPLH Maximum Propagation
CL 50 pF
2.0V
63
175
220
263
ns
Delay, LE to Q
CL 150 pF
2.0V
110
225
280
338
ns
CL 50 pF
4.5V
25
35
44
52
ns
CL 150 pF
4.5V
35
45
56
68
ns
CL 50 pF
6.0V
21
30
37
45
ns
CL 150 pF
6.0V
28
39
49
59
ns
tPZH, tPZL Maximum Output
RL 1 k:
Enable Time
CL 50 pF
2.0V
50
150
188
225
ns
CL 150 pF
2.0V
80
200
250
300
ns
CL 50 pF
4.5V
21
30
37
45
ns
CL 150 pF
4.5V
30
40
50
60
ns
CL 50 pF
6.0V
19
26
31
39
ns
CL 150 pF
6.0V
26
35
44
53
ns
tPHZ, tPLZ Maximum Output Disable
RL 1 k:
2.0V
50
150
188
225
ns
Disable Time
CL 50 pF
4.5V
21
30
37
45
ns
6.0V
19
26
31
39
ns
tS
Minimum Set Up Time
2.0V
50
60
75
ns
4.5V
9
13
15
ns
6.0V
9
11
13
ns
tH
Minimum Hold Time
2.0V
5
ns
4.5V
5
ns
6.0V
5
ns
tW
Minimum Pulse Width
2.0V
30
80
100
120
ns
4.5V
10
16
20
24
ns
6.0V
9
14
18
20
ns
tTHL, tTLH Maximum Output Rise
CL 50 pF
2.0V
25
60
75
90
ns
and Fall Time
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
CPD
Power Dissipation
(per latch)
Capacitance (Note 5)
OC
VCC
30
pF
OC
GND
50
pF
CIN
Maximum Input Capacitance
5
10
pF
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