參數(shù)資料
型號: MM74HC139MX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 編、解碼器及復(fù)用、解復(fù)用
中文描述: HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: 0.150 INCH, MS-012AC, SOIC-16
文件頁數(shù): 5/7頁
文件大?。?/td> 242K
代理商: MM74HC139MX
MM74HC139
Dual
2-T
o-4
Line
Decoder
1983 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HC139 Rev. 1.3
5
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6ns.
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6ns (unless otherwise specified).
Notes:
3. 4 levels of delay are A to Y1, Y3 and B to Y2, Y3.
4. 5 levels of delay are A to Y0, Y2 and B to Y0, Y1.
5. CPD determines the no load dynamic power consumption, PD = CPD VCC
2f + I
CC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol
Parameter
Conditions
Typ.
Guaranteed
Limit
Units
tPHL, tPLH
Maximum Propagation Delay, Binary Select
to any Output 4 levels of delay
18
30
ns
tPHL, tPLH
Maximum Propagation Delay, Binary Select
to any Output 5 levels of delay
28
38
ns
tPHL, tPLH
Maximum Propagation Delay, Enable to any
Output
19
30
ns
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = –40
to 85°C
TA = –55
to 125°C
Units
Typ.
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay Binary Select to any
Output 4 levels of delay
(3)
2.0V
110
175
219
254
ns
4.5V
22
35
44
51
6.0V
18
30
38
44
tPHL, tPLH
Maximum Propagation
Delay Binary Select to any
Output 5 levels of delay
(4)
2.0V
165
220
275
320
ns
4.5V
33
44
55
64
6.0V
28
38
47
54
tPHL, tPLH
Maximum Propagation
Delay Enable to any Output
2.0V
115
175
219
254
ns
4.5V
23
35
44
51
6.0V
19
30
38
44
tTLH, tTLH
Maximum Output Rise and
Fall Time
2.0V
30
75
95
110
ns
4.5V
8
15
19
22
6.0V
7
13
16
19
CIN
Maximum Input Capacitance
3
10
pF
CPD
Power Dissipation
Capacitance(5)
(5)
75
pF
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