參數(shù)資料
型號: MM74HC00SJ
廠商: Fairchild Semiconductor
文件頁數(shù): 1/9頁
文件大?。?/td> 0K
描述: IC GATE NAND QUAD 2-INP 14-SOP
標(biāo)準(zhǔn)包裝: 47
系列: 74HC
邏輯類型: 與非門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 5.2mA,5.2mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時的最大傳播延遲: 15ns @ 6V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 管件
MM74HC00
Quad
2-Input
NAND
Gate
1983 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HC00 Rev. 1.3.0
February 2008
MM74HC00
Quad 2-Input NAND Gate
Features
Typical propagation delay: 8ns
Wide power supply range: 2V–6V
Low quiescent current: 20A maximum (74HC Series)
Low input current: 1A maximum
Fanout of 10 LS-TTL loads
General Description
The MM74HC00 NAND gates utilize advanced silicon-
gate CMOS technology to achieve operating speeds
similar to LS-TTL gates with the low power consumption
of standard CMOS integrated circuits. All gates have
buffered outputs. All devices have high noise immunity
and the ability to drive 10 LS-TTL loads. The 74HC logic
family is functionally as well as pin-out compatible with
the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to VCC and ground.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
Order Number
Package
Number
Package Description
MM74HC00M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC00SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC00MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC00N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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