參數(shù)資料
型號(hào): MM74C93J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 通用總線功能
英文描述: 4-Bit Decade, Binary Counter
中文描述: CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14
封裝: CERAMIC, DIP-14
文件頁(yè)數(shù): 1/7頁(yè)
文件大小: 55K
代理商: MM74C93J
October 1987
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005889.prf
www.fairchildsemi.com
MM74C90 MM74C93
4-Bit Decade Counter 4-Bit Binary Counter
General Description
The MM74C90 decade counter and the MM74C93 binary
counter and complementary MOS (CMOS) integrated cir-
cuits constructed with N- and P-channel enhancement
mode transistors. The 4-bit decade counter can reset to
zero or preset to nine by applying appropriate logic level on
the R
01
, R
02
, R
91
and R
92
inputs. Also, a separate flip-flop
on the A-bit enables the user to operate it as a divide-by-2,
5 or 10 frequency counter. The 4-bit binary counter can be
reset to zero by applying high logic level on inputs R
01
and
R
02
, and a separate flip-flop on the A-bit enables the user
to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the input pulse.
All inputs are protected against static discharge damage.
Features
I
Wide supply voltage range:
I
Guaranteed noise margin:
I
High noise immunity:
3V to 15V
1V
0.45 V
CC
(typ.)
I
Low power compatibility:
Fan out of 2 TTL driving 74L
I
The MM74C93 follows the MM74L93 Pinout
Ordering Code:
Connection Diagrams
Pin Assignments for DIP
MM74C90
Top View
MM74C93
Top View
Order Number
MM74C90N
MM74C93N
Package Number
N14A
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
相關(guān)PDF資料
PDF描述
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