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then raising them to complete the write. Even though CE and
WE are interchangeable, CE is usually derived from the ad-
dress decoding logic and WE is connected to the CPU write
strobe. Other than the slight timing differences between the
MM74C911 and the MM74C912/MM74C917, the only other
major microprocessor interfacing differences are that the
MM74C912/MM74C917 have an additional digit address bit
which must be connected to the microprocessors address
bus, and the MM74C911 has eight data inputs whereas the
MM74C912/MM74C917 have only five.
A. Interfacing to the INS8080
These controllers can be connected to the INS8080/
INS8224/INS8238 CPU group with no external logic if no
more than a minimal amount of address decoding is re-
quired. Since the INS8080 has a separate memory and I/O
port address spaces, one of the I/O port address bits could
be directly connected to the CE input. Figure 27 illustrates
this using an MM74C911. Whenever an OUT instruction is
executed causing the I/OW (INS8080 write enable signal) to
go low and the address is such that A7 is low, A0 A1 will se-
lect the digit to be written. If more decoding is required, some
external gating logic may be added to the CE input.
The MM74C912/MM74C917 would be interfaced by con-
necting the A, B, C, D and DP to bit D0–D4 of the data bus
and connecting K1–K3 to A
–A
. Writing data to these con-
trollers would be the same as writing to the MM74C911.
B. Interfacing to the Z80
To connect these display controllers to the Z80 microproces-
sor, only a minor modification to the INS8080 need be made.
The Z80 control signals are slightly different from the
INS8080. Instead of the INS8080 I/O write strobe, the Z80
has an I/O request line (IOREQ ), which goes low to indicate
an I/O port is to be accessed, and a write (WR ) strobe which
indicates that a memory or I/O write is to be done. By
OR-ing, these together an equivalent I/OW signal is gener-
ated as shown in Figure 28
C. Interfacing to the NSC800
The NSC800 has very different timing because the lower
eight address bits and the data bus are multiplexed. But
when connecting the display controllers as I/O ports, the in-
terface is only slightly different from the INS8080 design.
When an I/O instruction is executed, the port address that
appears on A0–A7 is duplicated on A8–A15, and this ad-
dress can be used directly. The controller WE input must be
decoded from a WR (write enable) and IO/M (I/O or memory
enable) as shown in Figure 29 Note that since the NSC800
is a CMOS microprocessor, no pull-up resistors are needed.
Figure 29 uses address bit A15 which is equivalent to bit A7
on the previous examples. As with the previous examples, if
more address decoding is required, either gates or decoders
could be connected to the CE input.
D. Interfacing to the 6800
When using the INS8080, Z80, or NSC800, these proces-
sors have separate I/O and memory address spaces. This
usually allows simpler interfaces to be designed. The 6800
has no separate I/O addressing so I/O ports are usually
mapped into a small block of memory. This requires more
address decoding to ensure that memory and I/O don’t over-
lap.
Figure 30 shows a DM8131 6-bit address bus comparator
whose B
inputs are a combination ofA15–A12 address bits,
the
Φ
(6800 system clock) and the VMA (Valid Memory Ac-
cess) control signal. When these inputs equal the corre-
sponding T
inputs, the output goes low. The 6800 R/W sig-
nal is connected to the WE .
E. Interfacing to the INS8060/INS8070
Like the 6800, the INS8060/8070 series of microprocessors
don’t have any separate I/O addressing, so the MM74C911/
MM74C912/MM74C917 must be memory addressed, but
unlike the 6800 both the INS8070 series and the INS8060
have separate read/write strobes, which can simplify inter-
facing the display controllers. Figure 31 illustrates a typical
INS8060 interface. The NWDS (write enable) is directly con-
nected to the MM74C912s WE input and the DM8131 pro-
vides the address decoding for the controller. The INS8060
has only 12 address bits (unless using paged addressing) so
bits A
6
–A
11
are decoded by the comparator.
The INS8070 series microprocessor has the identical NWDS
signal but has 16 address bits. Thus Figure 31 would con-
nect the A10–A15 address bits to the DM8131.
AN006030-28
FIGURE 26. MM74C911/MM74C912/MM74C917 Timing Diagram (See data sheets for numbers)
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