參數(shù)資料
型號: MM54HC390J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 計數(shù)器
英文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, CDIP16
封裝: DIP-16
文件頁數(shù): 3/8頁
文件大?。?/td> 149K
代理商: MM54HC390J
AC Electrical Characteristics MM54HC390MM74HC390
VCCe5V TAe25 C CLe15 pF tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency Clock A or B
50
30
MHz
tPHL tPLH
Maximum Propagation Delay Clock A to QA Output
12
20
ns
tPHL tPLH
Maximum Propagation Delay Clock A to QC
32
50
ns
(QA Connected to Clock B)
tPHL tPLH
Maximum Propagation Delay Clock B to QB or QD
15
21
ns
tPHL tPLH
Maximum Propagation Delay Clock B to QC
20
32
ns
tPHL
Maximum Propagation Delay Clear to any Output
15
28
ns
tREM
Minimum Removal Time Clear to Clock
b
25
ns
tW
Minimum Pulse Width Clear or Clock
10
16
ns
AC Electrical Characteristics CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
20V
5
4
3
MHz
Frequency
45V
27
21
18
MHz
60V
31
24
20
MHz
tPHL tPLH
Maximum Propagation
20V
45
120
150
180
ns
Delay Clock A to QA
45V
15
24
30
35
ns
60V
13
21
26
31
ns
tPHL tPLH
Maximum Propagation
20V
100
290
360
430
ns
Delay Clock A to QC
45V
35
58
72
87
ns
(QA Connected to Clock B)
60V
30
50
62
75
ns
tPHL tPLH
Maximum Propagation
20V
50
130
160
195
ns
Delay Clock B to QB or
45V
16
26
33
39
ns
QD
60V
13
22
28
33
ns
tPHL tPLH
Maximum Propagation
20V
60
185
230
280
ns
Delay Clock B to QC
45V
20
37
46
55
ns
60V
17
32
40
48
ns
tPHL
Maximum Propagation
20V
55
165
210
250
ns
Delay Clear to any Q
45V
17
33
41
49
ns
60V
15
28
35
42
ns
tREM
Minimum Removal Time
20V
25
ns
Clear to Clock
45V
5
ns
60V
5
ns
tW
Minimum Pulse Width
20V
30
80
100
120
ns
Clear or Clock
45V
10
16
20
24
ns
60V
9
14
18
20
ns
tTHL tTLH
Maximum Output Rise
20V
30
75
95
110
ns
and Fall Time
45V
8
15
19
22
ns
60V
7
13
16
19
ns
tr tf
Maximum Input Rise
20V
1000
ns
and Fall Time
45V
500
ns
60V
400
ns
CPD
Power Dissipation
(per counter)
55
pF
Capacitance (Note 5)
CIN
Maximum Input Capacitance
5
10
pF
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3
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